[llvm] 70fdd9f - [GlobalISel] Check whether `G_CTLZ` is legal in `matchUMulHToLShr` (#126457)
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Sun Feb 9 21:11:12 PST 2025
Author: Shilei Tian
Date: 2025-02-10T00:11:09-05:00
New Revision: 70fdd9f0a24154b63169c66aff1ddc4507db6034
URL: https://github.com/llvm/llvm-project/commit/70fdd9f0a24154b63169c66aff1ddc4507db6034
DIFF: https://github.com/llvm/llvm-project/commit/70fdd9f0a24154b63169c66aff1ddc4507db6034.diff
LOG: [GlobalISel] Check whether `G_CTLZ` is legal in `matchUMulHToLShr` (#126457)
We need to check `G_CTLZ` because the combine uses `G_CTLZ` to get log
base 2,
and it is not always legal for on a target.
Fixes SWDEV-512440.
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
Modified:
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 4648414cc46aef6..0dfbb91f2ac5437 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5641,6 +5641,7 @@ bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) const {
Register RHS = MI.getOperand(2).getReg();
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
+ LLT RHSTy = MRI.getType(RHS);
LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty);
auto MatchPow2ExceptOne = [&](const Constant *C) {
if (auto *CI = dyn_cast<ConstantInt>(C))
@@ -5649,7 +5650,10 @@ bool CombinerHelper::matchUMulHToLShr(MachineInstr &MI) const {
};
if (!matchUnaryPredicate(MRI, RHS, MatchPow2ExceptOne, false))
return false;
- return isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, {Ty, ShiftAmtTy}});
+ // We need to check both G_LSHR and G_CTLZ because the combine uses G_CTLZ to
+ // get log base 2, and it is not always legal for on a target.
+ return isLegalOrBeforeLegalizer({TargetOpcode::G_LSHR, {Ty, ShiftAmtTy}}) &&
+ isLegalOrBeforeLegalizer({TargetOpcode::G_CTLZ, {RHSTy, RHSTy}});
}
void CombinerHelper::applyUMulHToLShr(MachineInstr &MI) const {
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
new file mode 100644
index 000000000000000..c237911319329a0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
@@ -0,0 +1,98 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -O0 -global-isel=true %s -o - | FileCheck %s
+
+define void @test(ptr %p) {
+; CHECK-LABEL: test:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mov_b32_e32 v2, v1
+; CHECK-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1 killed $exec
+; CHECK-NEXT: v_mov_b32_e32 v1, v2
+; CHECK-NEXT: s_mov_b32 s5, 16
+; CHECK-NEXT: s_mov_b32 s6, 0
+; CHECK-NEXT: v_mov_b32_e32 v2, s6
+; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v2, v2
+; CHECK-NEXT: v_rcp_iflag_f32_e64 v2, v2
+; CHECK-NEXT: s_mov_b32 s4, 0x4f7ffffe
+; CHECK-NEXT: v_mov_b32_e32 v3, s4
+; CHECK-NEXT: v_mul_f32_e64 v2, v2, v3
+; CHECK-NEXT: v_cvt_u32_f32_e64 v2, v2
+; CHECK-NEXT: s_mov_b32 s7, 0
+; CHECK-NEXT: v_mov_b32_e32 v3, s7
+; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3
+; CHECK-NEXT: v_add_u32_e64 v2, v2, v3
+; CHECK-NEXT: v_mov_b32_e32 v3, s5
+; CHECK-NEXT: v_mul_hi_u32 v2, v2, v3
+; CHECK-NEXT: s_mov_b32 s7, 2
+; CHECK-NEXT: v_mov_b32_e32 v3, s7
+; CHECK-NEXT: v_add_u32_e64 v2, v2, v3
+; CHECK-NEXT: v_mov_b32_e32 v3, s6
+; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v3, v3
+; CHECK-NEXT: v_rcp_iflag_f32_e64 v3, v3
+; CHECK-NEXT: v_mov_b32_e32 v4, s4
+; CHECK-NEXT: v_mul_f32_e64 v3, v3, v4
+; CHECK-NEXT: v_cvt_u32_f32_e64 v3, v3
+; CHECK-NEXT: s_mov_b32 s7, 0
+; CHECK-NEXT: v_mov_b32_e32 v4, s7
+; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT: v_add_u32_e64 v3, v3, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, s5
+; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
+; CHECK-NEXT: s_mov_b32 s7, 2
+; CHECK-NEXT: v_mov_b32_e32 v4, s7
+; CHECK-NEXT: v_add_u32_e64 v6, v3, v4
+; CHECK-NEXT: v_mov_b32_e32 v3, s6
+; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v3, v3
+; CHECK-NEXT: v_rcp_iflag_f32_e64 v3, v3
+; CHECK-NEXT: v_mov_b32_e32 v4, s4
+; CHECK-NEXT: v_mul_f32_e64 v3, v3, v4
+; CHECK-NEXT: v_cvt_u32_f32_e64 v3, v3
+; CHECK-NEXT: s_mov_b32 s7, 0
+; CHECK-NEXT: v_mov_b32_e32 v4, s7
+; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT: v_add_u32_e64 v3, v3, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, s5
+; CHECK-NEXT: v_mul_hi_u32 v3, v3, v4
+; CHECK-NEXT: s_mov_b32 s7, 2
+; CHECK-NEXT: v_mov_b32_e32 v4, s7
+; CHECK-NEXT: v_add_u32_e64 v3, v3, v4
+; CHECK-NEXT: v_mov_b32_e32 v4, s6
+; CHECK-NEXT: v_cvt_f32_ubyte0_e64 v4, v4
+; CHECK-NEXT: v_rcp_iflag_f32_e64 v4, v4
+; CHECK-NEXT: v_mov_b32_e32 v5, s4
+; CHECK-NEXT: v_mul_f32_e64 v4, v4, v5
+; CHECK-NEXT: v_cvt_u32_f32_e64 v4, v4
+; CHECK-NEXT: s_mov_b32 s4, 0
+; CHECK-NEXT: v_mov_b32_e32 v5, s4
+; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5
+; CHECK-NEXT: v_add_u32_e64 v4, v4, v5
+; CHECK-NEXT: v_mov_b32_e32 v5, s5
+; CHECK-NEXT: v_mul_hi_u32 v4, v4, v5
+; CHECK-NEXT: s_mov_b32 s4, 2
+; CHECK-NEXT: v_mov_b32_e32 v5, s4
+; CHECK-NEXT: v_add_u32_e64 v4, v4, v5
+; CHECK-NEXT: s_mov_b32 s4, 0xff
+; CHECK-NEXT: v_mov_b32_e32 v5, s4
+; CHECK-NEXT: v_mov_b32_e32 v7, s4
+; CHECK-NEXT: v_and_b32_e64 v7, v6, v7
+; CHECK-NEXT: s_mov_b32 s6, 8
+; CHECK-NEXT: v_mov_b32_e32 v6, s6
+; CHECK-NEXT: v_lshlrev_b32_e64 v6, v6, v7
+; CHECK-NEXT: v_and_or_b32 v2, v2, v5, v6
+; CHECK-NEXT: v_mov_b32_e32 v5, s4
+; CHECK-NEXT: v_and_b32_e64 v5, v3, v5
+; CHECK-NEXT: v_mov_b32_e32 v3, s5
+; CHECK-NEXT: v_lshlrev_b32_e64 v3, v3, v5
+; CHECK-NEXT: v_mov_b32_e32 v5, s4
+; CHECK-NEXT: v_and_b32_e64 v5, v4, v5
+; CHECK-NEXT: s_mov_b32 s4, 24
+; CHECK-NEXT: v_mov_b32_e32 v4, s4
+; CHECK-NEXT: v_lshlrev_b32_e64 v4, v4, v5
+; CHECK-NEXT: v_or3_b32 v2, v2, v3, v4
+; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %B = udiv <4 x i8> splat (i8 16), zeroinitializer
+ store <4 x i8> %B, ptr %p, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
new file mode 100644
index 000000000000000..00ead74cb37bb84
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=amdgpu-postlegalizer-combiner %s -o - | FileCheck %s
+
+---
+name: test
+tracksRegLiveness: true
+legalized: true
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; CHECK-LABEL: name: test
+ ; CHECK: liveins: $vgpr0, $vgpr1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+ ; CHECK-NEXT: [[UMULH:%[0-9]+]]:_(s32) = G_UMULH [[COPY]], [[C]]
+ ; CHECK-NEXT: $vgpr0 = COPY [[UMULH]](s32)
+ ; CHECK-NEXT: SI_RETURN implicit $vgpr0
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s32) = G_CONSTANT i32 4
+ %2:_(s32) = G_UMULH %0:_, %1:_
+ $vgpr0 = COPY %2:_(s32)
+ SI_RETURN implicit $vgpr0
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