[llvm] [ARM] Fix MRC cp10 and cp11 warning (PR #126407)

[via llvm-commits]

https://github.com/hstk30-hw created https://github.com/llvm/llvm-project/pull/126407

The MRC format is
    MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1,
        c_imm:$CRn, c_imm:$CRm, 0, pred:$p
The $cop is the second operand.

>From ec1673087ac1b732f4af1fb18af9e5c27a30acfa Mon Sep 17 00:00:00 2001
From: hstk30 <hanwei62 at huawei.com>
Date: Sun, 9 Feb 2025 15:24:25 +0800
Subject: [PATCH] [ARM] Fix MRC cp10 and cp11 warning

The MRC format is
    MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1,
        c_imm:$CRn, c_imm:$CRm, 0, pred:$p
The $cop is the second operand.
---
 llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 4 ++--
 llvm/test/MC/ARM/diagnostics.s                       | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 01a271327049f19..e1af3150a840317 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -77,8 +77,8 @@ static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
 static bool getMRCDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
                                   std::string &Info) {
   if (STI.hasFeature(llvm::ARM::HasV7Ops) &&
-      ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) ||
-       (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) {
+      ((MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 10) ||
+       (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 11))) {
     Info = "since v7, cp10 and cp11 are reserved for advanced SIMD or floating "
            "point instructions";
     return true;
diff --git a/llvm/test/MC/ARM/diagnostics.s b/llvm/test/MC/ARM/diagnostics.s
index fa23a7da1e40489..8f91d820bd80fcd 100644
--- a/llvm/test/MC/ARM/diagnostics.s
+++ b/llvm/test/MC/ARM/diagnostics.s
@@ -173,6 +173,10 @@
         @ p10 and p11 are reserved for NEON
         mcr p10, #2, r5, c1, c1, #4
         mcrr p11, #8, r5, r4, c1
+        mrc p10, #7, r5, c1, c1, #0
+        mrc p11, #7, r5, c1, c1, #0
+@ CHECK-WARN: warning: since v7, cp10 and cp11 are reserved for advanced SIMD or floating point instructions
+@ CHECK-WARN: warning: since v7, cp10 and cp11 are reserved for advanced SIMD or floating point instructions
 @ CHECK-WARN: warning: since v7, cp10 and cp11 are reserved for advanced SIMD or floating point instructions
 @ CHECK-WARN: warning: since v7, cp10 and cp11 are reserved for advanced SIMD or floating point instructions