[llvm] [RISCV] Attach an implicit source operand on vector copies (PR #126155)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=postrapseudos %s -o - | FileCheck %s
+
+---
+name:            copy
+isSSA:           false
+noVRegs:         true
+liveins:
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arsenm wrote:

Should set tracksRegLiveness 

https://github.com/llvm/llvm-project/pull/126155