[llvm] 564b9b7 - Revert "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126268)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 8 02:06:52 PST 2025
Author: Akshat Oke
Date: 2025-02-08T15:36:48+05:30
New Revision: 564b9b7f4db05b5ce3558041b164f21dfe051a91
URL: https://github.com/llvm/llvm-project/commit/564b9b7f4db05b5ce3558041b164f21dfe051a91
DIFF: https://github.com/llvm/llvm-project/commit/564b9b7f4db05b5ce3558041b164f21dfe051a91.diff
LOG: Revert "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (#126268)
This reverts commit 5aa4979c47255770cac7b557f3e4a980d0131d69 while I
investigate what's causing the compile-time regression.
Added:
Modified:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/include/llvm/InitializePasses.h
llvm/include/llvm/Passes/CodeGenPassBuilder.h
llvm/include/llvm/Passes/MachinePassRegistry.def
llvm/lib/CodeGen/CodeGen.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/RegAllocBasic.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/Passes/PassBuilder.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/test/CodeGen/AArch64/a55-fuse-address.mir
llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
llvm/test/CodeGen/AArch64/cluster-frame-index.mir
llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
llvm/test/CodeGen/AArch64/force-enable-intervals.mir
llvm/test/CodeGen/AArch64/machine-scheduler.mir
llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
llvm/test/CodeGen/AArch64/macro-fusion-last.mir
llvm/test/CodeGen/AArch64/misched-branch-targets.mir
llvm/test/CodeGen/AArch64/misched-bundle.mir
llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
llvm/test/CodeGen/AArch64/misched-move-imm.mir
llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
llvm/test/CodeGen/AArch64/sched-postidxalias.mir
llvm/test/CodeGen/AArch64/sched-print-cycle.mir
llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
llvm/test/CodeGen/AArch64/sve-aliasing.mir
llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
llvm/test/CodeGen/ARM/misched-branch-targets.mir
llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
llvm/test/CodeGen/RISCV/misched-postra-direction.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e1f1a1efecc724d..4762494e6ccb77d 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1385,24 +1385,6 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
-class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
- const TargetMachine *TM;
-
-public:
- MachineSchedulerPass(const TargetMachine *TM) : TM(TM) {}
- PreservedAnalyses run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM);
-};
-
-class PostMachineSchedulerPass
- : public PassInfoMixin<PostMachineSchedulerPass> {
- const TargetMachine *TM;
-
-public:
- PostMachineSchedulerPass(const TargetMachine *TM) : TM(TM) {}
- PreservedAnalyses run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM);
-};
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index b8df4d1ecab1d0f..6d74d7f24bf9a82 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &);
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
-void initializeMachineSchedulerLegacyPass(PassRegistry &);
+void initializeMachineSchedulerPass(PassRegistry &);
void initializeMachineSinkingPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
@@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &);
void initializePostDomViewerWrapperPassPass(PassRegistry &);
void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
-void initializePostMachineSchedulerLegacyPass(PassRegistry &);
+void initializePostMachineSchedulerPass(PassRegistry &);
void initializePostRAHazardRecognizerPass(PassRegistry &);
void initializePostRAMachineSinkingPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 1458318ff021a98..7f91dd7ebf49de9 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -50,7 +50,6 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
-#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
@@ -961,7 +960,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
if (getOptLevel() != CodeGenOptLevel::None &&
!TM.targetSchedulesPostRAScheduling()) {
if (Opt.MISchedPostRA)
- addPass(PostMachineSchedulerPass(&TM));
+ addPass(PostMachineSchedulerPass());
else
addPass(PostRASchedulerPass(&TM));
}
@@ -1145,7 +1144,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc(
addPass(RenameIndependentSubregsPass());
// PreRA instruction scheduling.
- addPass(MachineSchedulerPass(&TM));
+ addPass(MachineSchedulerPass());
if (derived().addRegAssignmentOptimized(addPass)) {
// Allow targets to expand pseudo instructions depending on the choice of
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index e6b4a4b0a56aeed..9f9922dfa5673c7 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -142,13 +142,11 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
-MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
-MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
@@ -245,11 +243,13 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
+DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
+DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 35df2a479a545e7..d69a24f00871eac 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeModuloScheduleTestPass(Registry);
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
- initializeMachineSchedulerLegacyPass(Registry);
+ initializeMachineSchedulerPass(Registry);
initializeMachineSinkingPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
@@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
- initializePostMachineSchedulerLegacyPass(Registry);
+ initializePostMachineSchedulerPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index df90077b15f331f..3f72e8486c06ef8 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -216,85 +216,67 @@ MachineSchedContext::~MachineSchedContext() {
namespace {
-/// Base class for the machine scheduler classes.
-class MachineSchedulerBase : public MachineSchedContext {
-protected:
- void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
-};
-
-/// Impl class for MachineScheduler.
-class MachineSchedulerImpl : public MachineSchedulerBase {
- MachineFunctionPass *P = nullptr;
- MachineFunctionAnalysisManager *MFAM = nullptr;
-
-public:
- MachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P);
- MachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM);
- bool run();
-
-protected:
- ScheduleDAGInstrs *createMachineScheduler();
-};
-
-/// Impl class for PostMachineScheduler.
-class PostMachineSchedulerImpl : public MachineSchedulerBase {
- MachineFunctionPass *P = nullptr;
- MachineFunctionAnalysisManager *MFAM = nullptr;
-
+/// Base class for a machine scheduler class that can run at any point.
+class MachineSchedulerBase : public MachineSchedContext,
+ public MachineFunctionPass {
public:
- PostMachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P);
- PostMachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM);
- bool run();
+ MachineSchedulerBase(char &ID) : MachineFunctionPass(ID) {}
protected:
- ScheduleDAGInstrs *createPostMachineScheduler();
+ void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
};
/// MachineScheduler runs after coalescing and before register allocation.
-class MachineSchedulerLegacy : public MachineFunctionPass {
+class MachineScheduler : public MachineSchedulerBase {
public:
- MachineSchedulerLegacy();
+ MachineScheduler();
+
void getAnalysisUsage(AnalysisUsage &AU) const override;
+
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+
+protected:
+ ScheduleDAGInstrs *createMachineScheduler();
};
/// PostMachineScheduler runs after shortly before code emission.
-class PostMachineSchedulerLegacy : public MachineFunctionPass {
+class PostMachineScheduler : public MachineSchedulerBase {
public:
- PostMachineSchedulerLegacy();
+ PostMachineScheduler();
+
void getAnalysisUsage(AnalysisUsage &AU) const override;
+
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+
+protected:
+ ScheduleDAGInstrs *createPostMachineScheduler();
};
} // end anonymous namespace
-char MachineSchedulerLegacy::ID = 0;
+char MachineScheduler::ID = 0;
-char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID;
+char &llvm::MachineSchedulerID = MachineScheduler::ID;
-INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE,
+INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
-MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) {
- initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
+MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
+ initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
}
-void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
+void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -307,24 +289,23 @@ void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-char PostMachineSchedulerLegacy::ID = 0;
+char PostMachineScheduler::ID = 0;
-char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID;
+char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
-INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched",
+INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched",
+INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
-PostMachineSchedulerLegacy::PostMachineSchedulerLegacy()
- : MachineFunctionPass(ID) {
- initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
+PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
+ initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
}
-void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
+void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -403,40 +384,18 @@ nextIfDebug(MachineBasicBlock::iterator I,
.getNonConstIterator();
}
-MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionPass *P)
- : P(P) {
- MF = &Func;
- MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- MDT = &P->getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
- AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
- LIS = &P->getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-}
-
-MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM)
- : MFAM(&MFAM) {
- MF = &Func;
- TM = TargetM;
- MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
- MDT = &MFAM.getResult<MachineDominatorTreeAnalysis>(Func);
- auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
- .getManager();
- AA = &FAM.getResult<AAManager>(Func.getFunction());
- LIS = &MFAM.getResult<LiveIntervalsAnalysis>(Func);
-}
-
/// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
-ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
+ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
// Select the scheduler, or set the default.
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
if (Ctor != useDefaultMachineSched)
return Ctor(this);
+ const TargetMachine &TM =
+ getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+
// Get the default scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -444,60 +403,14 @@ ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
return createGenericSchedLive(this);
}
-bool MachineSchedulerImpl::run() {
- if (VerifyScheduling) {
- LLVM_DEBUG(LIS->dump());
- const char *MSchedBanner = "Before machine scheduling.";
- if (P)
- MF->verify(P, MSchedBanner, &errs());
- else
- MF->verify(*MFAM, MSchedBanner, &errs());
- }
- RegClassInfo->runOnMachineFunction(*MF);
-
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
- scheduleRegions(*Scheduler, false);
-
- LLVM_DEBUG(LIS->dump());
- if (VerifyScheduling) {
- const char *MSchedBanner = "After machine scheduling.";
- if (P)
- MF->verify(P, MSchedBanner, &errs());
- else
- MF->verify(*MFAM, MSchedBanner, &errs());
- }
- return true;
-}
-
-PostMachineSchedulerImpl::PostMachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionPass *P)
- : P(P) {
- MF = &Func;
- MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
- AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
-}
-
-PostMachineSchedulerImpl::PostMachineSchedulerImpl(
- MachineFunction &Func, MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM)
- : MFAM(&MFAM) {
- MF = &Func;
- TM = TargetM;
- MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
- auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
- .getManager();
- AA = &FAM.getResult<AAManager>(Func.getFunction());
-}
-
/// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
/// the caller. We don't have a command line option to override the postRA
/// scheduler. The Target must configure it.
-ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
+ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
+ const TargetMachine &TM =
+ getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
// Get the postRA scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -505,30 +418,6 @@ ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
return createGenericSchedPostRA(this);
}
-bool PostMachineSchedulerImpl::run() {
- if (VerifyScheduling) {
- const char *PostMSchedBanner = "Before post machine scheduling.";
- if (P)
- MF->verify(P, PostMSchedBanner, &errs());
- else
- MF->verify(*MFAM, PostMSchedBanner, &errs());
- }
-
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
- scheduleRegions(*Scheduler, true);
-
- if (VerifyScheduling) {
- const char *PostMSchedBanner = "After post machine scheduling.";
- if (P)
- MF->verify(P, PostMSchedBanner, &errs());
- else
- MF->verify(*MFAM, PostMSchedBanner, &errs());
- }
- return true;
-}
-
/// Top-level MachineScheduler pass driver.
///
/// Visit blocks in function order. Divide each block into scheduling regions
@@ -545,84 +434,72 @@ bool PostMachineSchedulerImpl::run() {
/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
/// design would be to split blocks at scheduling boundaries, but LLVM has a
/// general bias against block splitting purely for implementation simplicity.
-bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
+bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
+ if (skipFunction(mf.getFunction()))
return false;
if (EnableMachineSched.getNumOccurrences()) {
if (!EnableMachineSched)
return false;
- } else if (!MF.getSubtarget().enableMachineScheduler()) {
+ } else if (!mf.getSubtarget().enableMachineScheduler())
return false;
- }
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
+ LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
- MachineSchedulerImpl Impl(MF, this);
- return Impl.run();
-}
+ // Initialize the context of the pass.
+ MF = &mf;
+ MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-PreservedAnalyses
-MachineSchedulerPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- if (EnableMachineSched.getNumOccurrences()) {
- if (!EnableMachineSched)
- return PreservedAnalyses::all();
- } else if (!MF.getSubtarget().enableMachineScheduler()) {
- return PreservedAnalyses::all();
- }
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
+ if (VerifyScheduling) {
+ LLVM_DEBUG(LIS->dump());
+ MF->verify(this, "Before machine scheduling.", &errs());
+ }
+ RegClassInfo->runOnMachineFunction(*MF);
- MachineSchedulerImpl Impl(MF, MFAM, TM);
- bool Changed = Impl.run();
- if (!Changed)
- return PreservedAnalyses::all();
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
+ scheduleRegions(*Scheduler, false);
- PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
- PA.preserveSet<CFGAnalyses>();
- PA.preserve<SlotIndexesAnalysis>();
- PA.preserve<LiveIntervalsAnalysis>();
- return PA;
+ LLVM_DEBUG(LIS->dump());
+ if (VerifyScheduling)
+ MF->verify(this, "After machine scheduling.", &errs());
+ return true;
}
-bool PostMachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
+bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
+ if (skipFunction(mf.getFunction()))
return false;
if (EnablePostRAMachineSched.getNumOccurrences()) {
if (!EnablePostRAMachineSched)
return false;
- } else if (!MF.getSubtarget().enablePostRAMachineScheduler()) {
+ } else if (!mf.getSubtarget().enablePostRAMachineScheduler()) {
LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
return false;
}
- LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs()));
+ LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
- PostMachineSchedulerImpl Impl(MF, this);
- return Impl.run();
-}
+ // Initialize the context of the pass.
+ MF = &mf;
+ MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-PreservedAnalyses
-PostMachineSchedulerPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- if (EnablePostRAMachineSched.getNumOccurrences()) {
- if (!EnablePostRAMachineSched)
- return PreservedAnalyses::all();
- } else if (!MF.getSubtarget().enablePostRAMachineScheduler()) {
- LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
- return PreservedAnalyses::all();
- }
- LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; MF.print(dbgs()));
+ if (VerifyScheduling)
+ MF->verify(this, "Before post machine scheduling.", &errs());
- PostMachineSchedulerImpl Impl(MF, MFAM, TM);
- bool Changed = Impl.run();
- if (!Changed)
- return PreservedAnalyses::all();
+ // Instantiate the selected scheduler for this target, function, and
+ // optimization level.
+ std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
+ scheduleRegions(*Scheduler, true);
- PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
- PA.preserveSet<CFGAnalyses>();
- return PA;
+ if (VerifyScheduling)
+ MF->verify(this, "After post machine scheduling.", &errs());
+ return true;
}
/// Return true of the given instruction should not be included in a scheduling
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index 51e047b2fa3f0cc..e1f05406297d2d2 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -135,7 +135,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescerLegacy)
-INITIALIZE_PASS_DEPENDENCY(MachineSchedulerLegacy)
+INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 2e43ad78e5d9b8a..465c4e8feffbb6e 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -155,7 +155,7 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescerLegacy)
-INITIALIZE_PASS_DEPENDENCY(MachineSchedulerLegacy)
+INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 650d23ac1d5efab..e7ba7213a76feb1 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -119,7 +119,6 @@
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachinePostDominators.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineTraceMetrics.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index fffd30b26dc1d50..c6d36fde9730a31 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -69,7 +69,6 @@
#include "llvm/CodeGen/MIRParser/MIParser.h"
#include "llvm/CodeGen/MachineCSE.h"
#include "llvm/CodeGen/MachineLICM.h"
-#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -1932,7 +1931,6 @@ AMDGPUCodeGenPassBuilder::AMDGPUCodeGenPassBuilder(
GCNTargetMachine &TM, const CGPassBuilderOption &Opts,
PassInstrumentationCallbacks *PIC)
: CodeGenPassBuilder(TM, Opts, PIC) {
- Opt.MISchedPostRA = true;
Opt.RequiresCodeGenSCCOrder = true;
// Exceptions and StackMaps are not supported, so these passes will never do
// anything.
diff --git a/llvm/test/CodeGen/AArch64/a55-fuse-address.mir b/llvm/test/CodeGen/AArch64/a55-fuse-address.mir
index 3e1b6076f016793..4edff043a7b3e5d 100644
--- a/llvm/test/CodeGen/AArch64/a55-fuse-address.mir
+++ b/llvm/test/CodeGen/AArch64/a55-fuse-address.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s
-# RUN: llc -o - %s -mtriple=aarch64 -passes=machine-scheduler | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
diff --git a/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir b/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
index 3a33291cbf8e0c1..e578b5d7f04f341 100644
--- a/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
+++ b/llvm/test/CodeGen/AArch64/ampere1-sched-add.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -run-pass=machine-scheduler %s -o - | FileCheck %s
-# RUN: llc -passes=machine-scheduler %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/cluster-frame-index.mir b/llvm/test/CodeGen/AArch64/cluster-frame-index.mir
index 5d761f10be3b22e..37ab9418f4dbdc9 100644
--- a/llvm/test/CodeGen/AArch64/cluster-frame-index.mir
+++ b/llvm/test/CodeGen/AArch64/cluster-frame-index.mir
@@ -1,5 +1,4 @@
#RUN: llc -mtriple=aarch64-- -mcpu=cyclone -run-pass machine-scheduler -o - %s | FileCheck %s
-#RUN: llc -mtriple=aarch64-- -mcpu=cyclone -passes=machine-scheduler -o - %s | FileCheck %s
---
name: merge_stack
# CHECK-LABEL: name: merge_stack
diff --git a/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir b/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
index 5655bfa5d294599..4bf8afff90d4cae 100644
--- a/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
+++ b/llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir
@@ -1,15 +1,9 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=true \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
-
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=false\
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NODUMP
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 -misched-dump-reserved-cycles=false\
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NODUMP
-
# REQUIRES: asserts
---
name: f
diff --git a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
index c90d6bd3cb420f8..bff6d1d71b7c44b 100644
--- a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
+++ b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir
@@ -4,34 +4,17 @@
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
# RUN: 2>&1 | FileCheck %s --check-prefix=TOP --strict-whitespace
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
-# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
-# RUN: 2>&1 | FileCheck %s --check-prefix=TOP --strict-whitespace
-
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
# RUN: 2>&1 | FileCheck %s --check-prefix=BOTTOM --strict-whitespace
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
-# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
-# RUN: 2>&1 | FileCheck %s --check-prefix=BOTTOM --strict-whitespace
-
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
# RUN: -sched-print-cycles=true -misched-dump-schedule-trace=true \
# RUN: 2>&1 | FileCheck %s --check-prefix=BIDIRECTIONAL
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -sched-print-cycles=true -misched-dump-schedule-trace=true \
-# RUN: 2>&1 | FileCheck %s --check-prefix=BIDIRECTIONAL
-
# REQUIRES: asserts, aarch64-registered-target
---
name: f
diff --git a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
index 8d47eee1c8e1937..a53d4e7480307dc 100644
--- a/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
+++ b/llvm/test/CodeGen/AArch64/force-enable-intervals.mir
@@ -3,21 +3,11 @@
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
-# RUN: -misched-dump-reserved-cycles=true \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s
-
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
# RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler \
# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
-# RUN: -misched-dump-reserved-cycles=true -sched-model-force-enable-intervals=true \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -o - %s 2>&1 -misched-prera-direction=topdown | FileCheck %s --check-prefix=FORCE
-
# REQUIRES: asserts, aarch64-registered-target
---
name: f
diff --git a/llvm/test/CodeGen/AArch64/machine-scheduler.mir b/llvm/test/CodeGen/AArch64/machine-scheduler.mir
index ba2c2b33d8e92bb..6c0222f4fdd7883 100644
--- a/llvm/test/CodeGen/AArch64/machine-scheduler.mir
+++ b/llvm/test/CodeGen/AArch64/machine-scheduler.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -passes=machine-scheduler -o - %s | FileCheck %s
--- |
define i64 @load_imp-def(ptr nocapture %P, i32 %v) {
diff --git a/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir b/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
index 2f0d19fec07d931..8c5a85a4e7a6141 100644
--- a/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
+++ b/llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir
@@ -1,7 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+fuse-addsub-2reg-const1 -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,FUSION
-# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+fuse-addsub-2reg-const1 -passes=postmisched | FileCheck %s --check-prefixes=CHECK,FUSION
# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-fuse-addsub-2reg-const1 -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION
-# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-fuse-addsub-2reg-const1 -passes=postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION
---
# CHECK-LABEL: name: addsub2reg
# CHECK: $w8 = ADDWrr killed renamable $w0, killed renamable $w1
diff --git a/llvm/test/CodeGen/AArch64/macro-fusion-last.mir b/llvm/test/CodeGen/AArch64/macro-fusion-last.mir
index affd2bb039e96c0..14937a4794e9613 100644
--- a/llvm/test/CodeGen/AArch64/macro-fusion-last.mir
+++ b/llvm/test/CodeGen/AArch64/macro-fusion-last.mir
@@ -1,7 +1,5 @@
# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+arith-bcc-fusion -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,FUSION
-# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+arith-bcc-fusion -passes=postmisched | FileCheck %s --check-prefixes=CHECK,FUSION
# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-arith-bcc-fusion -run-pass postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION
-# RUN: llc -o - %s -mtriple=aarch64-- -mattr=-arith-bcc-fusion -passes=postmisched | FileCheck %s --check-prefixes=CHECK,NOFUSION
# Make sure the last instruction is correctly macro-fused when scheduling
# top-down (post-ra).
---
diff --git a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
index 954082631bdbfaa..40f148438e537d2 100644
--- a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
+++ b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
@@ -1,9 +1,6 @@
# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
-# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -passes=postmisched %s | FileCheck %s
-
# REQUIRES: asserts
# -misched=shuffle is only available with assertions enabled
diff --git a/llvm/test/CodeGen/AArch64/misched-bundle.mir b/llvm/test/CodeGen/AArch64/misched-bundle.mir
index 8463cb038a3bcc2..ac6112e8c60efaf 100644
--- a/llvm/test/CodeGen/AArch64/misched-bundle.mir
+++ b/llvm/test/CodeGen/AArch64/misched-bundle.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a510 -passes=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK: SU(0): renamable $z0 = LD1H renamable $p0, renamable $x1, renamable $x10 :: (load unknown-size, align 1)
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
index ca92fa14a3fa850..ea40f9e52dcd682 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
@@ -6,14 +6,6 @@
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
# RUN: | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -mcpu=cortex-a55 %s -o - 2>&1 \
-# RUN: -misched-dump-reserved-cycles=true \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler \
-# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
-# RUN: -misched-detail-resource-booking=true \
-# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-header-width=21 \
-# RUN: | FileCheck %s
-
# REQUIRES: asserts, aarch64-registered-target
--- |
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
index 2b34ca54f1e9752..9be91b8a01e86b6 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
@@ -5,13 +5,6 @@
# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
# RUN: 2>&1 | FileCheck %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=cortex-a55 \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-prera-direction=bottomup -sched-print-cycles=true \
-# RUN: -misched-dump-reserved-cycles=true -misched-detail-resource-booking=true\
-# RUN: -misched-dump-schedule-trace=true -misched-dump-schedule-trace-col-width=4 \
-# RUN: 2>&1 | FileCheck %s
-
# REQUIRES: asserts, aarch64-registered-target
---
name: f
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
index 60c0026d394667e..62276779d142399 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir
@@ -1,7 +1,5 @@
# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -run-pass=machine-scheduler -misched-print-dags | FileCheck %s
-# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -passes=machine-scheduler -misched-print-dags | FileCheck %s
# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -run-pass=machine-scheduler -misched-print-dags | FileCheck %s
-# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=exynos-m4 -passes=machine-scheduler -misched-print-dags | FileCheck %s
# REQUIRES: asserts
---
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir b/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
index 82498164c6ad560..b0450c5b8c01bd7 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir
@@ -1,5 +1,4 @@
# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=cortex-x1 -run-pass=machine-scheduler
-# RUN: llc -o /dev/null 2>&1 %s -mtriple aarch64-unknown -mcpu=cortex-x1 -passes=machine-scheduler
# Just ensure this doesn't crash.
---
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir b/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
index e6613536157261f..623a8221f5ed2fa 100644
--- a/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
+++ b/llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir
@@ -1,9 +1,6 @@
# RUN: llc -o /dev/null %s -run-pass=machine-scheduler -mtriple aarch64-- -mattr=-fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE
# RUN: llc -o /dev/null %s -run-pass=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES
# RUN: llc -o /dev/null %s -run-pass=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+fuse-crypto-eor,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES,FUSECRYPTO
-# RUN: llc -o /dev/null %s -passes=machine-scheduler -mtriple aarch64-- -mattr=-fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,NOFUSE
-# RUN: llc -o /dev/null %s -passes=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES
-# RUN: llc -o /dev/null %s -passes=machine-scheduler -mtriple aarch64-- -mattr=+fuse-aes,+fuse-crypto-eor,+crypto -misched-print-dags 2>&1 | FileCheck %s --check-prefixes=CHECK,FUSEAES,FUSECRYPTO
# REQUIRES: asserts
name: func
diff --git a/llvm/test/CodeGen/AArch64/misched-move-imm.mir b/llvm/test/CodeGen/AArch64/misched-move-imm.mir
index 65608bb5f1a1c43..b5ff01b3c5b136d 100644
--- a/llvm/test/CodeGen/AArch64/misched-move-imm.mir
+++ b/llvm/test/CodeGen/AArch64/misched-move-imm.mir
@@ -1,5 +1,4 @@
# RUN: llc -run-pass=machine-scheduler -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 %s -o /dev/null 2>&1
-# RUN: llc -passes=machine-scheduler -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 %s -o /dev/null 2>&1
# Just ensure this doesn't crash. Ensures in the neoverse-v2
# scheduling model we don't attempt to treat the first input
# operand of MOVZXi as an immediate operand.
diff --git a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
index 17a6cf7e6faa93e..0b14ceeef9a09a6 100644
--- a/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
+++ b/llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir
@@ -1,5 +1,4 @@
# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s
-# RUN: llc -mcpu=exynos-m5 -mtriple=aarch64 -enable-misched -passes=machine-scheduler -debug-only=machine-scheduler %s -o /dev/null 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK-LABEL: ********** MI Scheduling **********
diff --git a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
index b652d2463fc12d6..b04fd89b796ba7a 100644
--- a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
+++ b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir
@@ -3,21 +3,11 @@
# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
-# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s
-
# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \
# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s
-# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s \
-# RUN: -misched-prera-direction=topdown -sched-print-cycles=true \
-# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s
-
# REQUIRES: asserts, aarch64-registered-target
---
name: test
diff --git a/llvm/test/CodeGen/AArch64/sched-postidxalias.mir b/llvm/test/CodeGen/AArch64/sched-postidxalias.mir
index 02256ca30d84299..98ee0fa21b2dd5e 100644
--- a/llvm/test/CodeGen/AArch64/sched-postidxalias.mir
+++ b/llvm/test/CodeGen/AArch64/sched-postidxalias.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=aarch64 -mcpu=cortex-a55 -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
# REQUIRES: asserts
# Both the accesses should have an offset of 0
diff --git a/llvm/test/CodeGen/AArch64/sched-print-cycle.mir b/llvm/test/CodeGen/AArch64/sched-print-cycle.mir
index d58037e98777307..59c51571df74b8d 100644
--- a/llvm/test/CodeGen/AArch64/sched-print-cycle.mir
+++ b/llvm/test/CodeGen/AArch64/sched-print-cycle.mir
@@ -1,15 +1,9 @@
# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
-# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=true \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
-
# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \
# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES
-# RUN: llc -mtriple=arm64-apple-macos -mcpu=apple-m1 -sched-print-cycles=false \
-# RUN: -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES
-
# REQUIRES: asserts
---
name: mul_mul
diff --git a/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir b/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
index 66680af3f856b31..65ec43407413f2e 100644
--- a/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
+++ b/llvm/test/CodeGen/AArch64/scheduledag-constreg.mir
@@ -1,5 +1,4 @@
# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s
-# RUN: llc -o /dev/null %s -mtriple=aarch64-- -passes=machine-scheduler -enable-misched -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts
--- |
define void @func() { ret void }
diff --git a/llvm/test/CodeGen/AArch64/sve-aliasing.mir b/llvm/test/CodeGen/AArch64/sve-aliasing.mir
index 34a08adc417cf61..3b7c9fefa5277ed 100644
--- a/llvm/test/CodeGen/AArch64/sve-aliasing.mir
+++ b/llvm/test/CodeGen/AArch64/sve-aliasing.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s
-# RUN: llc -o - %s -mtriple=aarch64 -passes=machine-scheduler | FileCheck %s
---
name: scalable_v16i1
diff --git a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
index 1c4093b2feb9b00..82ee173e1225638 100644
--- a/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
+++ b/llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir
@@ -1,7 +1,5 @@
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s
-# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -verify-misched -o /dev/null %s 2>&1 | FileCheck %s
-
# CHECK: *** Bad machine code: No live subrange at use ***
# CHECK-NEXT: - function: at_least_one_value_should_be_defined_by_this_mask
# CHECK-NEXT: - basic block: %bb.0
diff --git a/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir b/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
index 1ae544f3c074a0a..0d84dc0bdc53eff 100644
--- a/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
+++ b/llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: cluster_flat_loads
# GCN: FLAT_LOAD_DWORD %0, 0
diff --git a/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir b/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
index b38dc4d21c10c9b..4945c7020ca18cc 100644
--- a/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
+++ b/llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -o - %s | FileCheck %s
# The DBG_VALUE in bb.5 ends a scheduling region, and its uses should
# not be tracked like a normal instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
index 156979d6d06a57e..8a1c68b3f661509 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck %s
--- |
declare void @llvm.dbg.value(metadata, metadata, metadata) #0
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
index d415346b49b2851..19071be7ebde439 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK: ********** MI Scheduling **********
diff --git a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
index 170672dc4af647d..4f15e0ef689775b 100644
--- a/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
+++ b/llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK: All regions recorded, starting actual scheduling.
diff --git a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
index 204912b4d4881a2..962d49df8509e03 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
+++ b/llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=tonga -passes=machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: flat_load_clustering
# GCN: FLAT_LOAD_DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir b/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
index 78f21ef6610f2b3..d57450baea911a5 100644
--- a/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
+++ b/llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir
@@ -1,8 +1,6 @@
# REQUIRES: asserts
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -passes=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -amdgpu-use-amdgpu-trackers=1 -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN-GCNTRACKER %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -passes=machine-scheduler -amdgpu-use-amdgpu-trackers=1 -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN-GCNTRACKER %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -verify-misched -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-misched -run-pass=machine-scheduler -amdgpu-use-amdgpu-trackers=1 -verify-misched -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck -check-prefix=GCN-GCNTRACKER %s
--- |
define amdgpu_kernel void @high-RP-reschedule() { ret void }
diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
index 5dc6d2ee8f695b6..e32de1e42aac467 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule -verify-machineinstrs %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck -check-prefix=DEBUG %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule %s -o - -debug-only=machine-scheduler 2>&1 | FileCheck -check-prefix=DEBUG %s
# REQUIRES: asserts
--- |
diff --git a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
index 9991cb1837e01ce..fb65d80c46e06f7 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX908 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler -amdgpu-disable-unclustered-high-rp-reschedule %s -o - | FileCheck -check-prefix=GFX908 %s
---
name: test_occ_10_max_occ_no_sink
diff --git a/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir b/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
index ffc86dc5eee6f7e..2aa430400e49ae2 100644
--- a/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
+++ b/llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn -mcpu=tahiti -passes=machine-scheduler -o - %s | FileCheck -check-prefix=GCN %s
# GCN-LABEL: name: cluster_add_addc
# GCN: S_NOP 0, implicit-def $vcc
diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
index c90975959c3f491..c933fb0de586407 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -passes=machine-scheduler -verify-misched -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
# This would assert that a dead def should have no uses, but the dead
# def and use have
diff erent subreg indices.
diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
index 2cd78062ccbd75c..add7825a224ed00 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=machine-scheduler %s -o - | FileCheck %s
# The sequence of DBG_VALUEs forms a scheduling region with 0 real
# instructions. The RegPressure tracker would end up skipping over any
diff --git a/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir b/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
index f797b01d49bf862..3fdb0c7c0885b4e 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -passes=machine-scheduler -verify-misched -o - %s | FileCheck %s
# This would hang after removing edges from the SCHED_BARRIER since the number
# of Preds/Succs would be left in an inconsistent state.
diff --git a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
index 3254f5e45e4f4a4..09037709d51d8b9 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
@@ -1,5 +1,4 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass=machine-scheduler -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -passes=machine-scheduler -o - %s | FileCheck %s
--- |
%struct.widget.0 = type { float, i32, i32 }
diff --git a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
index 3ca61d26e8e4240..6796391aba6751c 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-misched -passes=machine-scheduler -o - %s | FileCheck %s
---
name: handleMoveUp_incorrect_interval
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
index 099cfc4f1dd5486..0b1fd441256d821 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
@@ -1,8 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=machine-scheduler -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -passes=machine-scheduler -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=machine-scheduler -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=machine-scheduler -o - %s | FileCheck %s
# Make sure FP mode is not a hard scheduling boundary
---
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir b/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
index 88e11c9ce3d1d77..e67036f0bbbea24 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
+++ b/llvm/test/CodeGen/AMDGPU/schedule-barrier.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=machine-scheduler -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=machine-scheduler -o - %s | FileCheck %s
---
# Check that the high latency loads are both scheduled first, before the
diff --git a/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir b/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
index 3091fe85fa8bccc..d8d4f5d0220c990 100644
--- a/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
+++ b/llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=postmisched -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -passes=postmisched -o - %s | FileCheck %s
---
name: test_xnull_256
body: |
diff --git a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
index 1bee32f4c90cda0..0a47b87b422dd4a 100644
--- a/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
+++ b/llvm/test/CodeGen/ARM/cortex-m7-wideops.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple arm-arm-eabi -mcpu=cortex-m7 -verify-machineinstrs -run-pass=postmisched %s -o - | FileCheck %s
-# RUN: llc -mtriple arm-arm-eabi -mcpu=cortex-m7 -passes=postmisched %s -o - | FileCheck %s
---
name: test_groups
alignment: 2
diff --git a/llvm/test/CodeGen/ARM/misched-branch-targets.mir b/llvm/test/CodeGen/ARM/misched-branch-targets.mir
index 610344f8440014a..d828d9e5162731f 100644
--- a/llvm/test/CodeGen/ARM/misched-branch-targets.mir
+++ b/llvm/test/CodeGen/ARM/misched-branch-targets.mir
@@ -1,7 +1,5 @@
# RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
-# RUN: llc -o - -passes=machine-scheduler -misched=shuffle %s | FileCheck %s
# RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
-# RUN: llc -o - -passes=postmisched %s | FileCheck %s
# REQUIRES: asserts
# -misched=shuffle is only available with assertions enabled
diff --git a/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir b/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
index 8bdbe288d98e60f..627e5534754800f 100644
--- a/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
+++ b/llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -run-pass=postmisched -o - %s | FileCheck %s
-# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -passes=postmisched -o - %s | FileCheck %s
---
# Check that postmisched's TopDepthReduce heuristic moves the MULLD later
# because of the dependency on x5
diff --git a/llvm/test/CodeGen/RISCV/misched-postra-direction.mir b/llvm/test/CodeGen/RISCV/misched-postra-direction.mir
index e4b934c3036aea5..2cca042bebee624 100644
--- a/llvm/test/CodeGen/RISCV/misched-postra-direction.mir
+++ b/llvm/test/CodeGen/RISCV/misched-postra-direction.mir
@@ -11,19 +11,6 @@
# RUN: -misched-dump-schedule-trace -misched-postra-direction=bidirectional \
# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BIDIRECTIONAL %s
-# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \
-# RUN: -enable-post-misched -debug-only=machine-scheduler \
-# RUN: -misched-dump-schedule-trace -misched-postra-direction=topdown \
-# RUN: -o - %s 2>&1 | FileCheck --check-prefix=TOPDOWN %s
-# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \
-# RUN: -enable-post-misched -debug-only=machine-scheduler \
-# RUN: -misched-dump-schedule-trace -misched-postra-direction=bottomup \
-# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BOTTOMUP %s
-# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -passes=postmisched \
-# RUN: -enable-post-misched -debug-only=machine-scheduler \
-# RUN: -misched-dump-schedule-trace -misched-postra-direction=bidirectional \
-# RUN: -o - %s 2>&1 | FileCheck --check-prefix=BIDIRECTIONAL %s
-
# REQUIRES: asserts
---
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