[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Luke Lau via llvm-commits]

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@@ -0,0 +1,154 @@
+//===- RISCVVMV0Elimination.cpp - VMV0 Elimination -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// Mask operands in vector pseudos have to be in v0. We select them as a virtual
+// register in the singleton vmv0 register class instead of copying them to $v0
+// straight away, to make optimizing masks easier.
+//
+// However the register allocator struggles with singleton register classes and
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lukel97 wrote:

My idea is that RISCVVMV0Elimination sits just before register allocation, after register coalescer. But instead of emitting copies to V0, it finds instructions with two or more distinct uses of VMV0.

Only one of the uses should need to be in VMV0, I.e the mask operand.

For the other uses, it would either inflate the uses to VR, or if not possible emit a COPY to VR. 

That way each instruction would have at most one use of VMV0, and this avoids the scenario that @arsenm was mentioning, which should be allocatable. 

I'm suggesting we could explore it as a follow up to this patch. 

https://github.com/llvm/llvm-project/pull/125026