[llvm] [RISCV] Attach an implicit source operand on vector copies (PR #126155)

[Min-Yih Hsu via llvm-commits]

https://github.com/mshockwave updated https://github.com/llvm/llvm-project/pull/126155

>From 1ec60d69bd450aed3e03fe45b1c8b474bdee98e5 Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Thu, 6 Feb 2025 15:40:22 -0800
Subject: [PATCH 1/2] [RISCV] Attach an implicit source operand on vector
 copies

Somtimes when we're breaking up a large vector copy into several smaller
ones, not every single smaller source registers are initialized at the
time when the original COPY happens, and the verifier will not be
pleased when seeing the smaller copies reading from an undef register.
This patch is a workaround for the said issue by attaching an implicit
read of the source operand on the newly generated copies.

This is tested by llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll which
would have crashed without this fix when LLVM_EXPENSIVE_CHECK is
enabled.

Co-Authored-By: Craig Topper <craig.topper at sifive.com>
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 12a7af075081360..47d6a5f4f95dfec 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -437,6 +437,11 @@ void RISCVInstrInfo::copyPhysRegVector(
       MIB.addReg(RISCV::VL, RegState::Implicit);
       MIB.addReg(RISCV::VTYPE, RegState::Implicit);
     }
+    // Add an implicit read of the original source to silence the verifier
+    // in the cases where some of the smaller VRs we're copying from might be
+    // undef, caused by the fact that the original, larger source VR might not
+    // be fully initialized at the time this COPY happens.
+    MIB.addReg(SrcReg, RegState::Implicit);
 
     // If we are copying reversely, we should decrease the encoding.
     SrcEncoding += (ReversedCopy ? -NumCopied : NumCopied);

>From aa8e9acd645d48fb971825f42a913a275c016b2c Mon Sep 17 00:00:00 2001
From: Min-Yih Hsu <min.hsu at sifive.com>
Date: Fri, 7 Feb 2025 17:11:41 -0800
Subject: [PATCH 2/2] fixup! Add MIR test

---
 .../test/CodeGen/RISCV/postra-copy-expand.mir | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/postra-copy-expand.mir

diff --git a/llvm/test/CodeGen/RISCV/postra-copy-expand.mir b/llvm/test/CodeGen/RISCV/postra-copy-expand.mir
new file mode 100644
index 000000000000000..e5b85659a0340c8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/postra-copy-expand.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=postrapseudos %s -o - | FileCheck %s
+
+---
+name:            copy
+isSSA:           false
+noVRegs:         true
+liveins:
+  - { reg: '$v0', virtual-reg: '' }
+body:             |
+  bb.0:
+    liveins: $v0
+
+    ; CHECK-LABEL: name: copy
+    ; CHECK: liveins: $v0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $vtype, implicit $v14_v15_v16_v17_v18
+    ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2, implicit $vtype, implicit $v14_v15_v16_v17_v18
+    ; CHECK-NEXT: $v24 = VMV1R_V $v18, implicit $vtype, implicit $v14_v15_v16_v17_v18, implicit $vtype
+    ; CHECK-NEXT: PseudoRET implicit $v0
+    renamable $v20_v21_v22_v23_v24 = COPY renamable $v14_v15_v16_v17_v18, implicit $vtype
+    PseudoRET implicit $v0
+
+...