[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Philip Reames via llvm-commits]

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@@ -1451,6 +1451,20 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+  // The partial reduction nodes sign or zero extend Input1 and Input2 to the
+  // element type of Accumulator before multiplying their results.
+  // This result is concatenated to the Accumulator, and this is then reduced,
+  // using addition, to the result type.
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preames wrote:

Then you need to say that clearly in the specification text.  At the moment, it looks like merely an unstated assumption, not a specifically reserved behavior.  The bit about the result only being valid for use by further reductions (i.e. non-order preserving operations) is really important to clearly say.

Seriously, I read your specification and didn't not understand this.  I doubt I'm the only one.  

https://github.com/llvm/llvm-project/pull/125207