[llvm] 5566bfa - [RISCV] Improve RISCVOperand Printing (#126179)

via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 7 10:58:02 PST 2025


Author: Sam Elliott
Date: 2025-02-07T10:57:59-08:00
New Revision: 5566bfa51e9baea0fdcd332198408f8cba39c0d0

URL: https://github.com/llvm/llvm-project/commit/5566bfa51e9baea0fdcd332198408f8cba39c0d0
DIFF: https://github.com/llvm/llvm-project/commit/5566bfa51e9baea0fdcd332198408f8cba39c0d0.diff

LOG: [RISCV] Improve RISCVOperand Printing (#126179)

We've gradually added more information to the RISCVOperand structure,
but the debug output has never caught up, which is quite confusing. This
adds printing for many of additional the fields in the structure, where
they are relevant.

In addition to this, we now have quite a lot of internal registers which
share names with each other - e.g. X0_H, X0_W, X0, X0_Pair all have the
same name - so also print the enum value to differentiate these.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index d050194142a475..ea6ca3b8f9a2dd 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1116,18 +1116,21 @@ struct RISCVOperand final : public MCParsedAsmOperand {
 
     switch (Kind) {
     case KindTy::Immediate:
-      OS << *getImm();
+      OS << "<imm: " << *Imm.Val << " " << (Imm.IsRV64 ? "rv64" : "rv32")
+         << ">";
       break;
     case KindTy::FPImmediate:
+      OS << "<fpimm: " << FPImm.Val << ">";
       break;
     case KindTy::Register:
-      OS << "<register " << RegName(getReg()) << ">";
+      OS << "<reg: " << RegName(Reg.RegNum) << " (" << Reg.RegNum
+         << (Reg.IsGPRAsFPR ? ") GPRasFPR>" : ")>");
       break;
     case KindTy::Token:
       OS << "'" << getToken() << "'";
       break;
     case KindTy::SystemRegister:
-      OS << "<sysreg: " << getSysReg() << '>';
+      OS << "<sysreg: " << getSysReg() << " (" << SysReg.Encoding << ")>";
       break;
     case KindTy::VType:
       OS << "<vtype: ";


        


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