[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

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@@ -1451,6 +1451,20 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+  // The partial reduction nodes sign or zero extend Input1 and Input2 to the
+  // element type of Accumulator before multiplying their results.
+  // This result is concatenated to the Accumulator, and this is then reduced,
+  // using addition, to the result type.
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paulwalker-arm wrote:

The intrinsic and matching ISD node are deliberate in not defining the order in which the elements are reduced because their output is only expected to feed into themselves or an equivalent vector.reduce operation and thus the ordering does not matter.  Essentially, add reductions can now be represented in LLVM as a two phase operation (one in-loop and the other out-of-loop) in the most relaxed way possible.

https://github.com/llvm/llvm-project/pull/125207