[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Philip Reames via llvm-commits]

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@@ -1451,6 +1451,20 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2)
+  // The partial reduction nodes sign or zero extend Input1 and Input2 to the
+  // element type of Accumulator before multiplying their results.
+  // This result is concatenated to the Accumulator, and this is then reduced,
+  // using addition, to the result type.
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preames wrote:

This specification is missing a really important detail.  Specifically, *which elements* are reduced via addition?  There's at least two reasonable choices here: adjacent, and subvector addition (i.e. every nth input).  Which is it?  Looking at the LangRef the associated intrinsic, this detail is missing there as well.  The specification needs updating.  

Looking at the implementation it is subvector-wise.  This needs explicitly stated.  

https://github.com/llvm/llvm-project/pull/125207