[llvm] Reduce shl64 to shl32 if shift range is [63-32] (PR #125574)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 10:28:07 PST 2025
================
@@ -0,0 +1,1318 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+;; Test reduction of:
+;;
+;; DST = shl i64 X, Y
+;;
+;; where Y is in the range [63-32] to:
+;;
+;; DST = [0, shl i32 X, (Y & 0x1F)]
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Test range with metadata
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; FIXME: This case should be reduced, but SelectionDAG::computeKnownBits() cannot
+; determine the minimum from metadata in this case. Match current results
+; for now.
+
+define i64 @shl_metadata(i64 noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dword v2, v[2:3]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load i64, ptr %arg1.ptr, !range !0
+ %shl = shl i64 %arg0, %shift.amt
+ ret i64 %shl
+}
+
+define <2 x i64> @shl_v2_metadata(<2 x i64> noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_v2_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !0
+ %shl = shl <2 x i64> %arg0, %shift.amt
+ ret <2 x i64> %shl
+}
+
+define <3 x i64> @shl_v3_metadata(<3 x i64> noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_v3_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dword v12, v[6:7] offset:16
+; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[6:7]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v12, v[4:5]
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !0
+ %shl = shl <3 x i64> %arg0, %shift.amt
+ ret <3 x i64> %shl
+}
+
+define <4 x i64> @shl_v4_metadata(<4 x i64> noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_v4_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[10:13], v[8:9]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[13:16], v[8:9] offset:16
+; CHECK-NEXT: ; kill: killed $vgpr8 killed $vgpr9
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v10, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v12, v[2:3]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v13, v[4:5]
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v15, v[6:7]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !0
+ %shl = shl <4 x i64> %arg0, %shift.amt
+ ret <4 x i64> %shl
+}
+
+define <5 x i64> @shl_v5_metadata(<5 x i64> noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_v5_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dword v19, v[10:11] offset:32
+; CHECK-NEXT: flat_load_dwordx4 v[12:15], v[10:11]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[15:18], v[10:11] offset:16
+; CHECK-NEXT: ; kill: killed $vgpr10 killed $vgpr11
+; CHECK-NEXT: v_lshlrev_b64 v[8:9], v19, v[8:9]
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v12, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v14, v[2:3]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v15, v[4:5]
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v17, v[6:7]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load <5 x i64>, ptr %arg1.ptr, !range !0
+ %shl = shl <5 x i64> %arg0, %shift.amt
+ ret <5 x i64> %shl
+}
+
+define <8 x i64> @shl_v8_metadata(<8 x i64> noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_v8_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[18:21], v[16:17]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v18, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v20, v[2:3]
+; CHECK-NEXT: flat_load_dwordx4 v[18:21], v[16:17] offset:16
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v18, v[4:5]
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v20, v[6:7]
+; CHECK-NEXT: flat_load_dwordx4 v[18:21], v[16:17] offset:32
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[8:9], v18, v[8:9]
+; CHECK-NEXT: flat_load_dwordx4 v[16:19], v[16:17] offset:48
+; CHECK-NEXT: v_lshlrev_b64 v[10:11], v20, v[10:11]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[12:13], v16, v[12:13]
+; CHECK-NEXT: v_lshlrev_b64 v[14:15], v18, v[14:15]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load <8 x i64>, ptr %arg1.ptr, !range !0
+ %shl = shl <8 x i64> %arg0, %shift.amt
+ ret <8 x i64> %shl
+}
+
+define <16 x i64> @shl_v16_metadata(<16 x i64> noundef %arg0, ptr %arg1.ptr) {
+; CHECK-LABEL: shl_v16_metadata:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
+; CHECK-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:4
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; CHECK-NEXT: s_waitcnt vmcnt(1)
+; CHECK-NEXT: flat_load_dwordx4 v[32:35], v[48:49]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[35:38], v[48:49] offset:16
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v32, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v34, v[2:3]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v35, v[4:5]
+; CHECK-NEXT: flat_load_dwordx4 v[32:35], v[48:49] offset:32
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v37, v[6:7]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[35:38], v[48:49] offset:48
+; CHECK-NEXT: v_lshlrev_b64 v[8:9], v32, v[8:9]
+; CHECK-NEXT: v_lshlrev_b64 v[10:11], v34, v[10:11]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[12:13], v35, v[12:13]
+; CHECK-NEXT: flat_load_dwordx4 v[32:35], v[48:49] offset:64
+; CHECK-NEXT: v_lshlrev_b64 v[14:15], v37, v[14:15]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[35:38], v[48:49] offset:80
+; CHECK-NEXT: v_lshlrev_b64 v[16:17], v32, v[16:17]
+; CHECK-NEXT: v_lshlrev_b64 v[18:19], v34, v[18:19]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[20:21], v35, v[20:21]
+; CHECK-NEXT: flat_load_dwordx4 v[32:35], v[48:49] offset:96
+; CHECK-NEXT: v_lshlrev_b64 v[22:23], v37, v[22:23]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: flat_load_dwordx4 v[35:38], v[48:49] offset:112
+; CHECK-NEXT: v_lshlrev_b64 v[24:25], v32, v[24:25]
+; CHECK-NEXT: v_lshlrev_b64 v[26:27], v34, v[26:27]
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_lshlrev_b64 v[28:29], v35, v[28:29]
+; CHECK-NEXT: v_lshlrev_b64 v[30:31], v37, v[30:31]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %shift.amt = load <16 x i64>, ptr %arg1.ptr, !range !0
+ %shl = shl <16 x i64> %arg0, %shift.amt
+ ret <16 x i64> %shl
+}
+
+!0 = !{i64 32, i64 64}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Test range with an "or X, 16"
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; These cases must not be reduced because the known minimum, 16, is not in range.
+
+define i64 @shl_or16(i64 noundef %arg0, i64 %shift_amt) {
+; CHECK-LABEL: shl_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v2, 16, v2
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or i64 %shift_amt, 16
+ %shl = shl i64 %arg0, %or
+ ret i64 %shl
+}
+
+define <2 x i64> @shl_v2_or16(<2 x i64> noundef %arg0, <2 x i64> %shift_amt) {
+; CHECK-LABEL: shl_v2_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v5, 16, v6
+; CHECK-NEXT: v_or_b32_e32 v4, 16, v4
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v5, v[2:3]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or <2 x i64> %shift_amt, splat (i64 16)
+ %shl = shl <2 x i64> %arg0, %or
+ ret <2 x i64> %shl
+}
+
+define <3 x i64> @shl_v3_or16(<3 x i64> noundef %arg0, <3 x i64> %shift_amt) {
+; CHECK-LABEL: shl_v3_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v7, 16, v10
+; CHECK-NEXT: v_or_b32_e32 v8, 16, v8
+; CHECK-NEXT: v_or_b32_e32 v6, 16, v6
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v8, v[2:3]
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v7, v[4:5]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or <3 x i64> %shift_amt, splat (i64 16)
+ %shl = shl <3 x i64> %arg0, %or
+ ret <3 x i64> %shl
+}
+
+define <4 x i64> @shl_v4_or16(<4 x i64> noundef %arg0, <4 x i64> %shift_amt) {
+; CHECK-LABEL: shl_v4_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v9, 16, v14
+; CHECK-NEXT: v_or_b32_e32 v11, 16, v12
+; CHECK-NEXT: v_or_b32_e32 v10, 16, v10
+; CHECK-NEXT: v_or_b32_e32 v8, 16, v8
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v11, v[4:5]
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v9, v[6:7]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or <4 x i64> %shift_amt, splat (i64 16)
+ %shl = shl <4 x i64> %arg0, %or
+ ret <4 x i64> %shl
+}
+
+define <5 x i64> @shl_v5_or16(<5 x i64> noundef %arg0, <5 x i64> %shift_amt) {
+; CHECK-LABEL: shl_v5_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v11, 16, v18
+; CHECK-NEXT: v_or_b32_e32 v13, 16, v16
+; CHECK-NEXT: v_or_b32_e32 v14, 16, v14
+; CHECK-NEXT: v_or_b32_e32 v12, 16, v12
+; CHECK-NEXT: v_or_b32_e32 v10, 16, v10
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v10, v[0:1]
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v12, v[2:3]
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v14, v[4:5]
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v13, v[6:7]
+; CHECK-NEXT: v_lshlrev_b64 v[8:9], v11, v[8:9]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or <5 x i64> %shift_amt, splat (i64 16)
+ %shl = shl <5 x i64> %arg0, %or
+ ret <5 x i64> %shl
+}
+
+define <8 x i64> @shl_v8_or16(<8 x i64> noundef %arg0, <8 x i64> %shift_amt) {
+; CHECK-LABEL: shl_v8_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v16
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v16, v[0:1]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v18
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v16, v[2:3]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v20
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v16, v[4:5]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v22
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v16, v[6:7]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v24
+; CHECK-NEXT: v_lshlrev_b64 v[8:9], v16, v[8:9]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v26
+; CHECK-NEXT: v_lshlrev_b64 v[10:11], v16, v[10:11]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v28
+; CHECK-NEXT: v_lshlrev_b64 v[12:13], v16, v[12:13]
+; CHECK-NEXT: v_or_b32_e32 v16, 16, v30
+; CHECK-NEXT: v_lshlrev_b64 v[14:15], v16, v[14:15]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or <8 x i64> %shift_amt, splat (i64 16)
+ %shl = shl <8 x i64> %arg0, %or
+ ret <8 x i64> %shl
+}
+
+define <16 x i64> @shl_v16_or16(<16 x i64> noundef %arg0, <16 x i64> %shift_amt) {
+; CHECK-LABEL: shl_v16_or16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[0:1], v31, v[0:1]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:12
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[2:3], v31, v[2:3]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[4:5], v31, v[4:5]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:28
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[6:7], v31, v[6:7]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:36
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[8:9], v31, v[8:9]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:44
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[10:11], v31, v[10:11]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:52
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[12:13], v31, v[12:13]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:60
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[14:15], v31, v[14:15]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:68
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[16:17], v31, v[16:17]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:76
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[18:19], v31, v[18:19]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:84
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[20:21], v31, v[20:21]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:92
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[22:23], v31, v[22:23]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:100
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[24:25], v31, v[24:25]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:108
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[26:27], v31, v[26:27]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:116
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v31, 16, v31
+; CHECK-NEXT: v_lshlrev_b64 v[28:29], v31, v[28:29]
+; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32
+; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:124
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_or_b32_e32 v32, 16, v32
+; CHECK-NEXT: v_lshlrev_b64 v[30:31], v32, v[30:31]
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %or = or <16 x i64> %shift_amt, splat (i64 16)
+ %shl = shl <16 x i64> %arg0, %or
+ ret <16 x i64> %shl
+}
+
+; test inreg
+
+define i64 @shl_or16_inreg(i64 noundef %arg0, i64 inreg %shift_amt) {
----------------
LU-JOHN wrote:
Used inreg for both inputs. Changed function name to use "sgpr" suffix. Could not find a way to return result in SGPR.
https://github.com/llvm/llvm-project/pull/125574
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