[llvm] InstCombine: teach foldICmpAddConstant about samesign (PR #126281)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 10:05:12 PST 2025
https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/126281
There are missed optimizations on samesign, due to the predicate being canonicalized into an equality before we get to our function.
>From cd008a7731b849c2503ac4b82f077c2cb04f9e65 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Fri, 7 Feb 2025 16:52:03 +0000
Subject: [PATCH 1/2] InstCombine: pre-commit icmp-add samesign tests
---
llvm/test/Transforms/InstCombine/icmp-add.ll | 328 ++++++++++++++++++-
1 file changed, 326 insertions(+), 2 deletions(-)
diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll
index a8cdf80948a8401..9767ea440d9f775 100644
--- a/llvm/test/Transforms/InstCombine/icmp-add.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-add.ll
@@ -1157,7 +1157,7 @@ bb:
ret i1 %i4
}
-; tests for sgt
+; tests for sgt, including samesign
define i1 @test_cvt_icmp7(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp7(
; CHECK-NEXT: bb:
@@ -1172,6 +1172,20 @@ bb:
ret i1 %i4
}
+define i1 @test_cvt_icmp7_samesign(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_cvt_icmp7_samesign(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 1
+ ret i1 %i4
+}
+
define i1 @test_zext_zext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_neg_2_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1185,6 +1199,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_zext_cvt_neg_2_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_2_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, -2
+ ret i1 %i4
+}
+
define i1 @test_zext_zext_cvt_neg_1_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_neg_1_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1198,6 +1225,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_zext_cvt_neg_1_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_1_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, -1
+ ret i1 %i4
+}
+
define i1 @test_zext_zext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_2_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1211,6 +1251,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_zext_cvt_2_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_2_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 2
+ ret i1 %i4
+}
+
define i1 @test_sext_sext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_neg_2_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1226,6 +1279,20 @@ bb:
ret i1 %i4
}
+define i1 @test_sext_sext_cvt_neg_2_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_2_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, -2
+ ret i1 %i4
+}
+
define i1 @test_sext_sext_cvt_0_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_0_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1239,6 +1306,20 @@ bb:
ret i1 %i4
}
+define i1 @test_sext_sext_cvt_0_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_0_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 0
+ ret i1 %i4
+}
+
define i1 @test_sext_sext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_2_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1252,6 +1333,20 @@ bb:
ret i1 %i4
}
+define i1 @test_sext_sext_cvt_2_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_2_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 2
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_neg_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_neg_2_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1265,6 +1360,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_neg_2_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_2_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[ARG1:%.*]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, -2
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_neg_1_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_neg_1_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1280,6 +1390,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_neg_1_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_1_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, -1
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_0_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_0_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1295,6 +1418,20 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_0_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_0_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 0
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_1_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_1_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1308,6 +1445,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_1_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_1_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[ARG1:%.*]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[TMP1]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 1
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_2_sgt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_2_sgt_icmp(
; CHECK-NEXT: bb:
@@ -1321,7 +1473,22 @@ bb:
ret i1 %i4
}
-; tests for slt
+define i1 @test_zext_sext_cvt_2_gt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_2_gt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = and i1 [[ARG1:%.*]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ugt i32 %i3, 2
+ ret i1 %i4
+}
+
+; tests for slt, including samesign
define i1 @test_zext_zext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_neg_2_slt_icmp(
; CHECK-NEXT: bb:
@@ -1335,6 +1502,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_zext_cvt_neg_2_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_2_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, -2
+ ret i1 %i4
+}
+
define i1 @test_zext_zext_cvt_neg_1_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_neg_1_slt_icmp(
; CHECK-NEXT: bb:
@@ -1348,6 +1528,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_zext_cvt_neg_1_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_neg_1_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 true
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, -1
+ ret i1 %i4
+}
+
define i1 @test_zext_zext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_zext_cvt_2_slt_icmp(
; CHECK-NEXT: bb:
@@ -1363,6 +1556,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_zext_cvt_2_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_zext_cvt_2_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = zext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, 2
+ ret i1 %i4
+}
+
define i1 @test_sext_sext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_neg_2_slt_icmp(
; CHECK-NEXT: bb:
@@ -1376,6 +1584,21 @@ bb:
ret i1 %i4
}
+define i1 @test_sext_sext_cvt_neg_2_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_neg_2_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, -2
+ ret i1 %i4
+}
+
define i1 @test_sext_sext_cvt_0_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_0_slt_icmp(
; CHECK-NEXT: bb:
@@ -1390,6 +1613,19 @@ bb:
ret i1 %i4
}
+define i1 @test_sext_sext_cvt_0_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_0_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, 0
+ ret i1 %i4
+}
+
define i1 @test_sext_sext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_2_slt_icmp(
; CHECK-NEXT: bb:
@@ -1403,6 +1639,21 @@ bb:
ret i1 %i4
}
+define i1 @test_sext_sext_cvt_2_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_sext_sext_cvt_2_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = sext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, 2
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_neg_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_neg_2_slt_icmp(
; CHECK-NEXT: bb:
@@ -1416,6 +1667,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_neg_2_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_2_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[ARG1_NOT:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG:%.*]], [[ARG1_NOT]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, -2
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_neg_1_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_neg_1_slt_icmp(
; CHECK-NEXT: bb:
@@ -1429,6 +1695,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_neg_1_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_neg_1_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG:%.*]], [[TMP0]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, -1
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_0_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_0_slt_icmp(
; CHECK-NEXT: bb:
@@ -1444,6 +1725,19 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_0_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_0_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: ret i1 false
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, 0
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_1_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_1_slt_icmp(
; CHECK-NEXT: bb:
@@ -1459,6 +1753,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_1_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_1_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG1:%.*]], [[ARG:%.*]]
+; CHECK-NEXT: [[I4:%.*]] = xor i1 [[TMP0]], true
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, 1
+ ret i1 %i4
+}
+
define i1 @test_zext_sext_cvt_2_slt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_2_slt_icmp(
; CHECK-NEXT: bb:
@@ -1472,6 +1781,21 @@ bb:
ret i1 %i4
}
+define i1 @test_zext_sext_cvt_2_lt_icmp(i1 %arg, i1 %arg1) {
+; CHECK-LABEL: @test_zext_sext_cvt_2_lt_icmp(
+; CHECK-NEXT: bb:
+; CHECK-NEXT: [[ARG1_NOT:%.*]] = xor i1 [[ARG1:%.*]], true
+; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG:%.*]], [[ARG1_NOT]]
+; CHECK-NEXT: ret i1 [[I4]]
+;
+bb:
+ %i = zext i1 %arg to i32
+ %i2 = sext i1 %arg1 to i32
+ %i3 = add i32 %i2, %i
+ %i4 = icmp samesign ult i32 %i3, 2
+ ret i1 %i4
+}
+
define i1 @test_cvt_icmp8(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_cvt_icmp8(
; CHECK-NEXT: bb:
>From b2312743959009703316adf6fe547192559d88b3 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Fri, 7 Feb 2025 18:00:43 +0000
Subject: [PATCH 2/2] InstCombine: teach foldICmpAddConstant about samesign
There are missed optimizations on samesign, due to the predicate being
canonicalized into an equality before we get to our function.
---
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp | 4 ++--
llvm/test/Transforms/InstCombine/icmp-add.ll | 7 ++-----
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 0feb6160b68fbb8..caa7643146cb21d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -3118,7 +3118,7 @@ Instruction *InstCombinerImpl::foldICmpAddConstant(ICmpInst &Cmp,
Value *Op0, *Op1;
Instruction *Ext0, *Ext1;
- const CmpInst::Predicate Pred = Cmp.getPredicate();
+ const CmpPredicate Pred = Cmp.getCmpPredicate();
if (match(Add,
m_Add(m_CombineAnd(m_Instruction(Ext0), m_ZExtOrSExt(m_Value(Op0))),
m_CombineAnd(m_Instruction(Ext1),
@@ -3133,7 +3133,7 @@ Instruction *InstCombinerImpl::foldICmpAddConstant(ICmpInst &Cmp,
Res += APInt(BW, isa<ZExtInst>(Ext0) ? 1 : -1, /*isSigned=*/true);
if (Op1Val)
Res += APInt(BW, isa<ZExtInst>(Ext1) ? 1 : -1, /*isSigned=*/true);
- return ICmpInst::compare(Res, C, Pred);
+ return ICmpInst::compare(Res, C, Pred.getPreferredSignedPredicate());
};
Table[0] = ComputeTable(false, false);
diff --git a/llvm/test/Transforms/InstCombine/icmp-add.ll b/llvm/test/Transforms/InstCombine/icmp-add.ll
index 9767ea440d9f775..cfa623754312891 100644
--- a/llvm/test/Transforms/InstCombine/icmp-add.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-add.ll
@@ -1336,8 +1336,7 @@ bb:
define i1 @test_sext_sext_cvt_2_gt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_sext_sext_cvt_2_gt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[I4:%.*]] = or i1 [[ARG1:%.*]], [[ARG:%.*]]
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = sext i1 %arg to i32
@@ -1476,9 +1475,7 @@ bb:
define i1 @test_zext_sext_cvt_2_gt_icmp(i1 %arg, i1 %arg1) {
; CHECK-LABEL: @test_zext_sext_cvt_2_gt_icmp(
; CHECK-NEXT: bb:
-; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[ARG:%.*]], true
-; CHECK-NEXT: [[I4:%.*]] = and i1 [[ARG1:%.*]], [[TMP0]]
-; CHECK-NEXT: ret i1 [[I4]]
+; CHECK-NEXT: ret i1 false
;
bb:
%i = zext i1 %arg to i32
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