[llvm] Revert "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" (PR #126268)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 09:24:01 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
@llvm/pr-subscribers-backend-arm
Author: Akshat Oke (optimisan)
<details>
<summary>Changes</summary>
This reverts commit 5aa4979c47255770cac7b557f3e4a980d0131d69 while I investigate what's causing the compile-time regression.
---
Patch is 63.68 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/126268.diff
56 Files Affected:
- (modified) llvm/include/llvm/CodeGen/MachineScheduler.h (-18)
- (modified) llvm/include/llvm/InitializePasses.h (+2-2)
- (modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+2-3)
- (modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+2-2)
- (modified) llvm/lib/CodeGen/CodeGen.cpp (+2-2)
- (modified) llvm/lib/CodeGen/MachineScheduler.cpp (+82-205)
- (modified) llvm/lib/CodeGen/RegAllocBasic.cpp (+1-1)
- (modified) llvm/lib/CodeGen/RegAllocGreedy.cpp (+1-1)
- (modified) llvm/lib/Passes/PassBuilder.cpp (-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp (-2)
- (modified) llvm/test/CodeGen/AArch64/a55-fuse-address.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/ampere1-sched-add.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/cluster-frame-index.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/dump-reserved-cycles.mir (-6)
- (modified) llvm/test/CodeGen/AArch64/dump-schedule-trace.mir (-17)
- (modified) llvm/test/CodeGen/AArch64/force-enable-intervals.mir (-10)
- (modified) llvm/test/CodeGen/AArch64/machine-scheduler.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/macro-fusion-addsub-2reg-const1.mir (-2)
- (modified) llvm/test/CodeGen/AArch64/macro-fusion-last.mir (-2)
- (modified) llvm/test/CodeGen/AArch64/misched-branch-targets.mir (-3)
- (modified) llvm/test/CodeGen/AArch64/misched-bundle.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir (-8)
- (modified) llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir (-7)
- (modified) llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir (-2)
- (modified) llvm/test/CodeGen/AArch64/misched-fusion-cmp.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/misched-fusion-crypto-eor.mir (-3)
- (modified) llvm/test/CodeGen/AArch64/misched-move-imm.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir (-10)
- (modified) llvm/test/CodeGen/AArch64/sched-postidxalias.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/sched-print-cycle.mir (-6)
- (modified) llvm/test/CodeGen/AArch64/scheduledag-constreg.mir (-1)
- (modified) llvm/test/CodeGen/AArch64/sve-aliasing.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir (-2)
- (modified) llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/dbg-value-ends-sched-region.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler-liveins.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/debug-value-scheduler.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/high-RP-reschedule.mir (+2-4)
- (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats-debug.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/machine-scheduler-sink-trivial-remats.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir (+1-2)
- (modified) llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/sched-barrier-hang-weak-dep.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir (-2)
- (modified) llvm/test/CodeGen/AMDGPU/schedule-barrier.mir (-1)
- (modified) llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir (-1)
- (modified) llvm/test/CodeGen/ARM/cortex-m7-wideops.mir (-1)
- (modified) llvm/test/CodeGen/ARM/misched-branch-targets.mir (-2)
- (modified) llvm/test/CodeGen/PowerPC/topdepthreduce-postra.mir (-1)
- (modified) llvm/test/CodeGen/RISCV/misched-postra-direction.mir (-13)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e1f1a1efecc724d..4762494e6ccb77d 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -1385,24 +1385,6 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);
-class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
- const TargetMachine *TM;
-
-public:
- MachineSchedulerPass(const TargetMachine *TM) : TM(TM) {}
- PreservedAnalyses run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM);
-};
-
-class PostMachineSchedulerPass
- : public PassInfoMixin<PostMachineSchedulerPass> {
- const TargetMachine *TM;
-
-public:
- PostMachineSchedulerPass(const TargetMachine *TM) : TM(TM) {}
- PreservedAnalyses run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM);
-};
} // end namespace llvm
#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index b8df4d1ecab1d0f..6d74d7f24bf9a82 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &);
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
-void initializeMachineSchedulerLegacyPass(PassRegistry &);
+void initializeMachineSchedulerPass(PassRegistry &);
void initializeMachineSinkingPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
@@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &);
void initializePostDomViewerWrapperPassPass(PassRegistry &);
void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
-void initializePostMachineSchedulerLegacyPass(PassRegistry &);
+void initializePostMachineSchedulerPass(PassRegistry &);
void initializePostRAHazardRecognizerPass(PassRegistry &);
void initializePostRAMachineSinkingPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 1458318ff021a98..7f91dd7ebf49de9 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -50,7 +50,6 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
-#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
@@ -961,7 +960,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
if (getOptLevel() != CodeGenOptLevel::None &&
!TM.targetSchedulesPostRAScheduling()) {
if (Opt.MISchedPostRA)
- addPass(PostMachineSchedulerPass(&TM));
+ addPass(PostMachineSchedulerPass());
else
addPass(PostRASchedulerPass(&TM));
}
@@ -1145,7 +1144,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc(
addPass(RenameIndependentSubregsPass());
// PreRA instruction scheduling.
- addPass(MachineSchedulerPass(&TM));
+ addPass(MachineSchedulerPass());
if (derived().addRegAssignmentOptimized(addPass)) {
// Allow targets to expand pseudo instructions depending on the choice of
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index e6b4a4b0a56aeed..9f9922dfa5673c7 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -142,13 +142,11 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
-MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
-MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
@@ -245,11 +243,13 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
+DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
+DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 35df2a479a545e7..d69a24f00871eac 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeModuloScheduleTestPass(Registry);
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
- initializeMachineSchedulerLegacyPass(Registry);
+ initializeMachineSchedulerPass(Registry);
initializeMachineSinkingPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
@@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
- initializePostMachineSchedulerLegacyPass(Registry);
+ initializePostMachineSchedulerPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index df90077b15f331f..3f72e8486c06ef8 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -216,85 +216,67 @@ MachineSchedContext::~MachineSchedContext() {
namespace {
-/// Base class for the machine scheduler classes.
-class MachineSchedulerBase : public MachineSchedContext {
-protected:
- void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
-};
-
-/// Impl class for MachineScheduler.
-class MachineSchedulerImpl : public MachineSchedulerBase {
- MachineFunctionPass *P = nullptr;
- MachineFunctionAnalysisManager *MFAM = nullptr;
-
-public:
- MachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P);
- MachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM);
- bool run();
-
-protected:
- ScheduleDAGInstrs *createMachineScheduler();
-};
-
-/// Impl class for PostMachineScheduler.
-class PostMachineSchedulerImpl : public MachineSchedulerBase {
- MachineFunctionPass *P = nullptr;
- MachineFunctionAnalysisManager *MFAM = nullptr;
-
+/// Base class for a machine scheduler class that can run at any point.
+class MachineSchedulerBase : public MachineSchedContext,
+ public MachineFunctionPass {
public:
- PostMachineSchedulerImpl(MachineFunction &Func, MachineFunctionPass *P);
- PostMachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM);
- bool run();
+ MachineSchedulerBase(char &ID) : MachineFunctionPass(ID) {}
protected:
- ScheduleDAGInstrs *createPostMachineScheduler();
+ void scheduleRegions(ScheduleDAGInstrs &Scheduler, bool FixKillFlags);
};
/// MachineScheduler runs after coalescing and before register allocation.
-class MachineSchedulerLegacy : public MachineFunctionPass {
+class MachineScheduler : public MachineSchedulerBase {
public:
- MachineSchedulerLegacy();
+ MachineScheduler();
+
void getAnalysisUsage(AnalysisUsage &AU) const override;
+
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+
+protected:
+ ScheduleDAGInstrs *createMachineScheduler();
};
/// PostMachineScheduler runs after shortly before code emission.
-class PostMachineSchedulerLegacy : public MachineFunctionPass {
+class PostMachineScheduler : public MachineSchedulerBase {
public:
- PostMachineSchedulerLegacy();
+ PostMachineScheduler();
+
void getAnalysisUsage(AnalysisUsage &AU) const override;
+
bool runOnMachineFunction(MachineFunction&) override;
static char ID; // Class identification, replacement for typeinfo
+
+protected:
+ ScheduleDAGInstrs *createPostMachineScheduler();
};
} // end anonymous namespace
-char MachineSchedulerLegacy::ID = 0;
+char MachineScheduler::ID = 0;
-char &llvm::MachineSchedulerID = MachineSchedulerLegacy::ID;
+char &llvm::MachineSchedulerID = MachineScheduler::ID;
-INITIALIZE_PASS_BEGIN(MachineSchedulerLegacy, DEBUG_TYPE,
+INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
-INITIALIZE_PASS_END(MachineSchedulerLegacy, DEBUG_TYPE,
+INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
-MachineSchedulerLegacy::MachineSchedulerLegacy() : MachineFunctionPass(ID) {
- initializeMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
+MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) {
+ initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
}
-void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
+void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -307,24 +289,23 @@ void MachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-char PostMachineSchedulerLegacy::ID = 0;
+char PostMachineScheduler::ID = 0;
-char &llvm::PostMachineSchedulerID = PostMachineSchedulerLegacy::ID;
+char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
-INITIALIZE_PASS_BEGIN(PostMachineSchedulerLegacy, "postmisched",
+INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
-INITIALIZE_PASS_END(PostMachineSchedulerLegacy, "postmisched",
+INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
"PostRA Machine Instruction Scheduler", false, false)
-PostMachineSchedulerLegacy::PostMachineSchedulerLegacy()
- : MachineFunctionPass(ID) {
- initializePostMachineSchedulerLegacyPass(*PassRegistry::getPassRegistry());
+PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
+ initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
}
-void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
+void PostMachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineDominatorTreeWrapperPass>();
AU.addRequired<MachineLoopInfoWrapperPass>();
@@ -403,40 +384,18 @@ nextIfDebug(MachineBasicBlock::iterator I,
.getNonConstIterator();
}
-MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionPass *P)
- : P(P) {
- MF = &Func;
- MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- MDT = &P->getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
- AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
- LIS = &P->getAnalysis<LiveIntervalsWrapperPass>().getLIS();
-}
-
-MachineSchedulerImpl::MachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM)
- : MFAM(&MFAM) {
- MF = &Func;
- TM = TargetM;
- MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
- MDT = &MFAM.getResult<MachineDominatorTreeAnalysis>(Func);
- auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
- .getManager();
- AA = &FAM.getResult<AAManager>(Func.getFunction());
- LIS = &MFAM.getResult<LiveIntervalsAnalysis>(Func);
-}
-
/// Instantiate a ScheduleDAGInstrs that will be owned by the caller.
-ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
+ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() {
// Select the scheduler, or set the default.
MachineSchedRegistry::ScheduleDAGCtor Ctor = MachineSchedOpt;
if (Ctor != useDefaultMachineSched)
return Ctor(this);
+ const TargetMachine &TM =
+ getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+
// Get the default scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM->createMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM.createMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -444,60 +403,14 @@ ScheduleDAGInstrs *MachineSchedulerImpl::createMachineScheduler() {
return createGenericSchedLive(this);
}
-bool MachineSchedulerImpl::run() {
- if (VerifyScheduling) {
- LLVM_DEBUG(LIS->dump());
- const char *MSchedBanner = "Before machine scheduling.";
- if (P)
- MF->verify(P, MSchedBanner, &errs());
- else
- MF->verify(*MFAM, MSchedBanner, &errs());
- }
- RegClassInfo->runOnMachineFunction(*MF);
-
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
- scheduleRegions(*Scheduler, false);
-
- LLVM_DEBUG(LIS->dump());
- if (VerifyScheduling) {
- const char *MSchedBanner = "After machine scheduling.";
- if (P)
- MF->verify(P, MSchedBanner, &errs());
- else
- MF->verify(*MFAM, MSchedBanner, &errs());
- }
- return true;
-}
-
-PostMachineSchedulerImpl::PostMachineSchedulerImpl(MachineFunction &Func,
- MachineFunctionPass *P)
- : P(P) {
- MF = &Func;
- MLI = &P->getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- TM = &P->getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
- AA = &P->getAnalysis<AAResultsWrapperPass>().getAAResults();
-}
-
-PostMachineSchedulerImpl::PostMachineSchedulerImpl(
- MachineFunction &Func, MachineFunctionAnalysisManager &MFAM,
- const TargetMachine *TargetM)
- : MFAM(&MFAM) {
- MF = &Func;
- TM = TargetM;
- MLI = &MFAM.getResult<MachineLoopAnalysis>(Func);
- auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(Func)
- .getManager();
- AA = &FAM.getResult<AAManager>(Func.getFunction());
-}
-
/// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
/// the caller. We don't have a command line option to override the postRA
/// scheduler. The Target must configure it.
-ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
+ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
+ const TargetMachine &TM =
+ getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
// Get the postRA scheduler set by the target for this function.
- ScheduleDAGInstrs *Scheduler = TM->createPostMachineScheduler(this);
+ ScheduleDAGInstrs *Scheduler = TM.createPostMachineScheduler(this);
if (Scheduler)
return Scheduler;
@@ -505,30 +418,6 @@ ScheduleDAGInstrs *PostMachineSchedulerImpl::createPostMachineScheduler() {
return createGenericSchedPostRA(this);
}
-bool PostMachineSchedulerImpl::run() {
- if (VerifyScheduling) {
- const char *PostMSchedBanner = "Before post machine scheduling.";
- if (P)
- MF->verify(P, PostMSchedBanner, &errs());
- else
- MF->verify(*MFAM, PostMSchedBanner, &errs());
- }
-
- // Instantiate the selected scheduler for this target, function, and
- // optimization level.
- std::unique_ptr<ScheduleDAGInstrs> Scheduler(createPostMachineScheduler());
- scheduleRegions(*Scheduler, true);
-
- if (VerifyScheduling) {
- const char *PostMSchedBanner = "After post machine scheduling.";
- if (P)
- MF->verify(P, PostMSchedBanner, &errs());
- else
- MF->verify(*MFAM, PostMSchedBanner, &errs());
- }
- return true;
-}
-
/// Top-level MachineScheduler pass driver.
///
/// Visit blocks in function order. Divide each block into scheduling regions
@@ -545,84 +434,72 @@ bool PostMachineSchedulerImpl::run() {
/// ScheduleDAGInstrs whenever adding or removing instructions. A much simpler
/// design would be to split blocks at scheduling boundaries, but LLVM has a
/// general bias against block splitting purely for implementation simplicity.
-bool MachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
- if (skipFunction(MF.getFunction()))
+bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
+ if (skipFunction(mf.getFunction()))
return false;
if (EnableMachineSched.getNumOccurrences()) {
if (!EnableMachineSched)
return false;
- } else if (!MF.getSubtarget().enableMachineScheduler()) {
+ } else if (!mf.getSubtarget().enableMachineScheduler())
return false;
- }
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
+ LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
- MachineSchedulerImpl Impl(MF, this);
- return Impl.run();
-}
+ // Initialize the context of the pass.
+ MF = &mf;
+ MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
-PreservedAnalyses
-MachineSchedulerPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- if (EnableMachineSched.getNumOccurrences()) {
- if (!EnableMachineSched)
- return PreservedAnalyses::all();
- } else if (!MF.getSubtarget().enableMachineScheduler()) {
- return PreservedAnalyses::all();
- }
+ LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- LLVM_DEBUG(dbgs() << "Before MISched:\n"; MF.print(dbgs()));
+ if (VerifyScheduling) {
+ LLVM_DEBUG(LIS->dump());
+ MF->verify(this, "Before machine scheduling.", &errs());
+ }
+ RegClassInfo->runOnMachineFunction(*MF);
- MachineSchedulerImpl Impl(MF, MFAM, TM);
- ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/126268
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