[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

================
@@ -2881,6 +2890,13 @@ SDValue DAGTypeLegalizer::PromoteIntOp_VECTOR_FIND_LAST_ACTIVE(SDNode *N,
   return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntOp_PARTIAL_REDUCE_MLA(SDNode *N) {
+  SmallVector<SDValue, 1> NewOps(N->ops());
+  NewOps[1] = GetPromotedInteger(N->getOperand(1));
+  NewOps[2] = GetPromotedInteger(N->getOperand(2));
----------------
paulwalker-arm wrote:

This is not safe because the signedness of the multiply operands is important and must be preserved.  You'll want something like:
```
if (N->getOpcode() == ISD::PARTIAL_REDUCE_SMLA) {
  NewOps[1] = SExtPromotedInteger(N->getOperand(1));
  NewOps[2] = SExtPromotedInteger(N->getOperand(2));
} else {
  NewOps[1] = ZExtPromotedInteger(N->getOperand(1));
  NewOps[2] = ZExtPromotedInteger(N->getOperand(2));
}
```

https://github.com/llvm/llvm-project/pull/125207