[llvm] 1f2c36a - [ARM] Reject fixed-point VCVT with different registers (#126232)
via llvm-commits
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Fri Feb 7 06:32:20 PST 2025
Author: Oliver Stannard
Date: 2025-02-07T14:32:15Z
New Revision: 1f2c36a879a604683da646a44f73bd6d90b61040
URL: https://github.com/llvm/llvm-project/commit/1f2c36a879a604683da646a44f73bd6d90b61040
DIFF: https://github.com/llvm/llvm-project/commit/1f2c36a879a604683da646a44f73bd6d90b61040.diff
LOG: [ARM] Reject fixed-point VCVT with different registers (#126232)
These instructions only have one register field in their encoding, so
both registers in the assembly must be the same.
Previously, we were accepting these instructions, but ignoring the
second register operand.
Fixes #126227
Added:
llvm/test/MC/ARM/vcvt-fixed-point-errors.s
Modified:
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/test/tools/llvm-mca/ARM/m55-fp.s
llvm/test/tools/llvm-mca/ARM/m7-fp.s
llvm/test/tools/llvm-mca/ARM/m85-fp.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index dad91c6a969e879..325dfb33762a663 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8652,6 +8652,37 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
"coprocessor must be configured as GCP");
break;
}
+
+ case ARM::VTOSHH:
+ case ARM::VTOUHH:
+ case ARM::VTOSLH:
+ case ARM::VTOULH:
+ case ARM::VTOSHS:
+ case ARM::VTOUHS:
+ case ARM::VTOSLS:
+ case ARM::VTOULS:
+ case ARM::VTOSHD:
+ case ARM::VTOUHD:
+ case ARM::VTOSLD:
+ case ARM::VTOULD:
+ case ARM::VSHTOH:
+ case ARM::VUHTOH:
+ case ARM::VSLTOH:
+ case ARM::VULTOH:
+ case ARM::VSHTOS:
+ case ARM::VUHTOS:
+ case ARM::VSLTOS:
+ case ARM::VULTOS:
+ case ARM::VSHTOD:
+ case ARM::VUHTOD:
+ case ARM::VSLTOD:
+ case ARM::VULTOD: {
+ if (Operands[MnemonicOpsEndInd]->getReg() !=
+ Operands[MnemonicOpsEndInd + 1]->getReg())
+ return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
+ "source and destination registers must be the same");
+ break;
+ }
}
return false;
diff --git a/llvm/test/MC/ARM/vcvt-fixed-point-errors.s b/llvm/test/MC/ARM/vcvt-fixed-point-errors.s
new file mode 100644
index 000000000000000..90e9da054a9081e
--- /dev/null
+++ b/llvm/test/MC/ARM/vcvt-fixed-point-errors.s
@@ -0,0 +1,51 @@
+// RUN: not llvm-mc -triple=armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s
+
+ vcvt.u16.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.s16.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.u32.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.s32.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.u16.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.s16.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.u32.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.s32.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.u16.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.s16.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.u32.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.s32.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f16.u16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f16.s16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f16.u32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f16.s32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f32.u16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f32.s16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f32.u32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f32.s32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f64.u16 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f64.s16 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f64.u32 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+ vcvt.f64.s32 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+
diff --git a/llvm/test/tools/llvm-mca/ARM/m55-fp.s b/llvm/test/tools/llvm-mca/ARM/m55-fp.s
index 6318cfa9d6e9cbf..1668f58c7937f32 100644
--- a/llvm/test/tools/llvm-mca/ARM/m55-fp.s
+++ b/llvm/test/tools/llvm-mca/ARM/m55-fp.s
@@ -21,30 +21,30 @@ vcmpe.f32 s1, #0.0
vcmpe.f64 d1, #0.0
vcvt.f32.f64 s1, d2
vcvt.f64.f32 d1, s1
-vcvt.f16.u16 s1, s2, #8
-vcvt.f16.s16 s1, s2, #8
-vcvt.f16.u32 s1, s2, #8
-vcvt.f16.s32 s1, s2, #8
-vcvt.u16.f16 s1, s2, #8
-vcvt.s16.f16 s1, s2, #8
-vcvt.u32.f16 s1, s2, #8
-vcvt.s32.f16 s1, s2, #8
-vcvt.f32.u16 s1, s2, #8
-vcvt.f32.s16 s1, s2, #8
-vcvt.f32.u32 s1, s2, #8
-vcvt.f32.s32 s1, s2, #8
-vcvt.u16.f32 s1, s2, #8
-vcvt.s16.f32 s1, s2, #8
-vcvt.u32.f32 s1, s2, #8
-vcvt.s32.f32 s1, s2, #8
-vcvt.f64.u16 d1, d2, #8
-vcvt.f64.s16 d1, d2, #8
-vcvt.f64.u32 d1, d2, #8
-vcvt.f64.s32 d1, d2, #8
-vcvt.u16.f64 d1, d2, #8
-vcvt.s16.f64 d1, d2, #8
-vcvt.u32.f64 d1, d2, #8
-vcvt.s32.f64 d1, d2, #8
+vcvt.f16.u16 s1, s1, #8
+vcvt.f16.s16 s1, s1, #8
+vcvt.f16.u32 s1, s1, #8
+vcvt.f16.s32 s1, s1, #8
+vcvt.u16.f16 s1, s1, #8
+vcvt.s16.f16 s1, s1, #8
+vcvt.u32.f16 s1, s1, #8
+vcvt.s32.f16 s1, s1, #8
+vcvt.f32.u16 s1, s1, #8
+vcvt.f32.s16 s1, s1, #8
+vcvt.f32.u32 s1, s1, #8
+vcvt.f32.s32 s1, s1, #8
+vcvt.u16.f32 s1, s1, #8
+vcvt.s16.f32 s1, s1, #8
+vcvt.u32.f32 s1, s1, #8
+vcvt.s32.f32 s1, s1, #8
+vcvt.f64.u16 d1, d1, #8
+vcvt.f64.s16 d1, d1, #8
+vcvt.f64.u32 d1, d1, #8
+vcvt.f64.s32 d1, d1, #8
+vcvt.u16.f64 d1, d1, #8
+vcvt.s16.f64 d1, d1, #8
+vcvt.u32.f64 d1, d1, #8
+vcvt.s32.f64 d1, d1, #8
vcvt.u32.f16 s1, s2
vcvt.s32.f16 s1, s2
vcvt.u32.f32 s1, s2
diff --git a/llvm/test/tools/llvm-mca/ARM/m7-fp.s b/llvm/test/tools/llvm-mca/ARM/m7-fp.s
index dcf9723461dec85..dba7ff92f30cb06 100644
--- a/llvm/test/tools/llvm-mca/ARM/m7-fp.s
+++ b/llvm/test/tools/llvm-mca/ARM/m7-fp.s
@@ -9,22 +9,22 @@ vcmp.f32 s1, s2
vcmp.f64 d1, d2
vcvt.f32.f64 s1, d2
vcvt.f64.f32 d1, s1
-vcvt.f32.u16 s1, s2, #8
-vcvt.f32.s16 s1, s2, #8
-vcvt.f32.u32 s1, s2, #8
-vcvt.f32.s32 s1, s2, #8
-vcvt.u16.f32 s1, s2, #8
-vcvt.s16.f32 s1, s2, #8
-vcvt.u32.f32 s1, s2, #8
-vcvt.s32.f32 s1, s2, #8
-vcvt.f64.u16 d1, d2, #8
-vcvt.f64.s16 d1, d2, #8
-vcvt.f64.u32 d1, d2, #8
-vcvt.f64.s32 d1, d2, #8
-vcvt.u16.f64 d1, d2, #8
-vcvt.s16.f64 d1, d2, #8
-vcvt.u32.f64 d1, d2, #8
-vcvt.s32.f64 d1, d2, #8
+vcvt.f32.u16 s1, s1, #8
+vcvt.f32.s16 s1, s1, #8
+vcvt.f32.u32 s1, s1, #8
+vcvt.f32.s32 s1, s1, #8
+vcvt.u16.f32 s1, s1, #8
+vcvt.s16.f32 s1, s1, #8
+vcvt.u32.f32 s1, s1, #8
+vcvt.s32.f32 s1, s1, #8
+vcvt.f64.u16 d1, d1, #8
+vcvt.f64.s16 d1, d1, #8
+vcvt.f64.u32 d1, d1, #8
+vcvt.f64.s32 d1, d1, #8
+vcvt.u16.f64 d1, d1, #8
+vcvt.s16.f64 d1, d1, #8
+vcvt.u32.f64 d1, d1, #8
+vcvt.s32.f64 d1, d1, #8
vcvt.u32.f32 s1, s2
vcvt.s32.f32 s1, s2
vcvt.u32.f64 s1, d2
diff --git a/llvm/test/tools/llvm-mca/ARM/m85-fp.s b/llvm/test/tools/llvm-mca/ARM/m85-fp.s
index edc46060fe0f397..0fc1b394de2dc19 100644
--- a/llvm/test/tools/llvm-mca/ARM/m85-fp.s
+++ b/llvm/test/tools/llvm-mca/ARM/m85-fp.s
@@ -21,30 +21,30 @@ vcmpe.f32 s1, #0.0
vcmpe.f64 d1, #0.0
vcvt.f32.f64 s1, d2
vcvt.f64.f32 d1, s1
-vcvt.f16.u16 s1, s2, #8
-vcvt.f16.s16 s1, s2, #8
-vcvt.f16.u32 s1, s2, #8
-vcvt.f16.s32 s1, s2, #8
-vcvt.u16.f16 s1, s2, #8
-vcvt.s16.f16 s1, s2, #8
-vcvt.u32.f16 s1, s2, #8
-vcvt.s32.f16 s1, s2, #8
-vcvt.f32.u16 s1, s2, #8
-vcvt.f32.s16 s1, s2, #8
-vcvt.f32.u32 s1, s2, #8
-vcvt.f32.s32 s1, s2, #8
-vcvt.u16.f32 s1, s2, #8
-vcvt.s16.f32 s1, s2, #8
-vcvt.u32.f32 s1, s2, #8
-vcvt.s32.f32 s1, s2, #8
-vcvt.f64.u16 d1, d2, #8
-vcvt.f64.s16 d1, d2, #8
-vcvt.f64.u32 d1, d2, #8
-vcvt.f64.s32 d1, d2, #8
-vcvt.u16.f64 d1, d2, #8
-vcvt.s16.f64 d1, d2, #8
-vcvt.u32.f64 d1, d2, #8
-vcvt.s32.f64 d1, d2, #8
+vcvt.f16.u16 s1, s1, #8
+vcvt.f16.s16 s1, s1, #8
+vcvt.f16.u32 s1, s1, #8
+vcvt.f16.s32 s1, s1, #8
+vcvt.u16.f16 s1, s1, #8
+vcvt.s16.f16 s1, s1, #8
+vcvt.u32.f16 s1, s1, #8
+vcvt.s32.f16 s1, s1, #8
+vcvt.f32.u16 s1, s1, #8
+vcvt.f32.s16 s1, s1, #8
+vcvt.f32.u32 s1, s1, #8
+vcvt.f32.s32 s1, s1, #8
+vcvt.u16.f32 s1, s1, #8
+vcvt.s16.f32 s1, s1, #8
+vcvt.u32.f32 s1, s1, #8
+vcvt.s32.f32 s1, s1, #8
+vcvt.f64.u16 d1, d1, #8
+vcvt.f64.s16 d1, d1, #8
+vcvt.f64.u32 d1, d1, #8
+vcvt.f64.s32 d1, d1, #8
+vcvt.u16.f64 d1, d1, #8
+vcvt.s16.f64 d1, d1, #8
+vcvt.u32.f64 d1, d1, #8
+vcvt.s32.f64 d1, d1, #8
vcvt.u32.f16 s1, s2
vcvt.s32.f16 s1, s2
vcvt.u32.f32 s1, s2
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