[llvm] [ARM] Reject fixed-point VCVT with different registers (PR #126232)

[Oliver Stannard via llvm-commits]

https://github.com/ostannard created https://github.com/llvm/llvm-project/pull/126232

These instructions only have one register field in their encoding, so both registers in the assembly must be the same.

Previously, we were accepting these instructions, but ignoring the second register operand.

Fixes #126227

>From 37f92d70fbc4e6d817fef72919a3aa3ce3785e3e Mon Sep 17 00:00:00 2001
From: Oliver Stannard <oliver.stannard at arm.com>
Date: Fri, 7 Feb 2025 11:23:46 +0000
Subject: [PATCH] [ARM] Reject fixed-point VCVT with different registers

These instructions only have one register field in their encoding, so
both registers in the assembly must be the same.
---
 .../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 31 +++++++++++
 llvm/test/MC/ARM/vcvt-fixed-point-errors.s    | 51 +++++++++++++++++++
 2 files changed, 82 insertions(+)
 create mode 100644 llvm/test/MC/ARM/vcvt-fixed-point-errors.s

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index dad91c6a969e879..325dfb33762a663 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8652,6 +8652,37 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
                    "coprocessor must be configured as GCP");
     break;
   }
+
+  case ARM::VTOSHH:
+  case ARM::VTOUHH:
+  case ARM::VTOSLH:
+  case ARM::VTOULH:
+  case ARM::VTOSHS:
+  case ARM::VTOUHS:
+  case ARM::VTOSLS:
+  case ARM::VTOULS:
+  case ARM::VTOSHD:
+  case ARM::VTOUHD:
+  case ARM::VTOSLD:
+  case ARM::VTOULD:
+  case ARM::VSHTOH:
+  case ARM::VUHTOH:
+  case ARM::VSLTOH:
+  case ARM::VULTOH:
+  case ARM::VSHTOS:
+  case ARM::VUHTOS:
+  case ARM::VSLTOS:
+  case ARM::VULTOS:
+  case ARM::VSHTOD:
+  case ARM::VUHTOD:
+  case ARM::VSLTOD:
+  case ARM::VULTOD: {
+    if (Operands[MnemonicOpsEndInd]->getReg() !=
+        Operands[MnemonicOpsEndInd + 1]->getReg())
+      return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
+                   "source and destination registers must be the same");
+    break;
+  }
   }
 
   return false;
diff --git a/llvm/test/MC/ARM/vcvt-fixed-point-errors.s b/llvm/test/MC/ARM/vcvt-fixed-point-errors.s
new file mode 100644
index 000000000000000..90e9da054a9081e
--- /dev/null
+++ b/llvm/test/MC/ARM/vcvt-fixed-point-errors.s
@@ -0,0 +1,51 @@
+// RUN: not llvm-mc -triple=armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s
+
+  vcvt.u16.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.s16.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.u32.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.s32.f16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.u16.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.s16.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.u32.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.s32.f32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.u16.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.s16.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.u32.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.s32.f64 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f16.u16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f16.s16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f16.u32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f16.s32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f32.u16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f32.s16 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f32.u32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f32.s32 s0, s1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f64.u16 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f64.s16 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f64.u32 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+  vcvt.f64.s32 d0, d1, #1
+// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
+