[llvm] Reduce shl64 to shl32 if shift range is [63-32] (PR #125574)

[Matt Arsenault via llvm-commits]

================
@@ -4040,19 +4040,35 @@ SDValue AMDGPUTargetLowering::splitBinaryBitConstantOpImpl(
 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
                                                 DAGCombinerInfo &DCI) const {
   EVT VT = N->getValueType(0);
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+  ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
+  SDLoc SL(N);
+  SelectionDAG &DAG = DCI.DAG;
 
-  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
-  if (!RHS)
+  if (!CRHS) {
+    // shl i64 X, Y -> [0, shl i32 X, (Y & 0x1F)]
+    if (VT == MVT::i64) {
+      KnownBits Known = DAG.computeKnownBits(RHS);
+      if (Known.getMinValue().getZExtValue() >= 32) {
+        SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, RHS);
+        const SDValue C31 = DAG.getConstant(31, SL, MVT::i32);
----------------
arsenm wrote:

Can you avoid hardcoding the 32s and do it in terms of the target type size? 

https://github.com/llvm/llvm-project/pull/125574