[llvm] [RISCV] Attach an implicit source operand on vector copies (PR #126155)

[Min-Yih Hsu via llvm-commits]

================
@@ -437,6 +437,11 @@ void RISCVInstrInfo::copyPhysRegVector(
       MIB.addReg(RISCV::VL, RegState::Implicit);
       MIB.addReg(RISCV::VTYPE, RegState::Implicit);
     }
+    // Add an implicit read of the original source to silence the verifier
+    // in the cases where some of the smaller VRs we're copying from might be
+    // undef, caused by the fact that the original, larger source VR might not
+    // be fully initialized at the time this COPY happens.
----------------
mshockwave wrote:

The case I saw was created by register coalescer where in generates something like this:
```
%8.sub_vrm2_0:vrn32 = ...
%15.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4:vrn3m2 = COPY %8.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
```
what happened was that the first instruction only initializes part of `%8` and the second one COPY from _another_ partially initialized (or partially undef) sub-register of `%8`. In this case we can't mark the source operand of COPY with `undef`. This COPY will eventually got broken down into smaller copies, in which one of those copies were copied from an undef register, hence the verifier error.

An alternative solution would be adding `undef` on source operand of the lowered, smaller copy instructions when needed. But that requires LiveIntervalsAnaysis. 

https://github.com/llvm/llvm-project/pull/126155