[llvm] [SelectionDAG] Wire up -gen-sdnode-info TableGen backend (PR #125358)

Sergei Barannikov via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 6 18:00:18 PST 2025


s-barannikov wrote:

> Have we ever verified normal (non-target) SDNodes using similar logics you put in SDNodeInfo::verifyNode?

This `verifySDNode` checks `BUILD_PAIR` and `BUILD_VECTOR`, and there are also some ad-hoc asserts in `SelectionDAG::getNode()`,  [example](https://github.com/llvm/llvm-project/blob/b7c8271601461e02fb567d6cd175fe20e123d78a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L6282).


https://github.com/llvm/llvm-project/pull/125358


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