[llvm] [SVE ACLE] Add `NodeMap[V]` for `svcount` in SelectionDAGBuilder (PR #126089)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: Da Li (李达) (dlee992)

<details>
<summary>Changes</summary>

As title. 
This PR comes from the discussion here: https://github.com/llvm/llvm-project/pull/69321#discussion_r1944048251.
I am willing to address any further comments/suggestions!

cc @<!-- -->paulwalker-arm 

---
Full diff: https://github.com/llvm/llvm-project/pull/126089.diff


1 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+3-2) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4e1ce6af3abc84..2c175ff621bea0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1893,8 +1893,9 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
 
     if (VT == MVT::aarch64svcount) {
       assert(C->isNullValue() && "Can only zero this target type!");
-      return DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT,
-                         DAG.getConstant(0, getCurSDLoc(), MVT::nxv16i1));
+      return NodeMap[V] =
+                 DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT,
+                             DAG.getConstant(0, getCurSDLoc(), MVT::nxv16i1));
     }
 
     if (VT.isRISCVVectorTuple()) {

``````````

</details>


https://github.com/llvm/llvm-project/pull/126089