[llvm] [SVE ACLE] Add `NodeMap[V]` for `svcount` in SelectionDAGBuilder (PR #126089)

[Da Li 李达 via llvm-commits]

https://github.com/dlee992 created https://github.com/llvm/llvm-project/pull/126089

As title. 
This PR comes from the discussion here: https://github.com/llvm/llvm-project/pull/69321#discussion_r1944048251.
I am willing to address any further comments/suggestions!

cc @paulwalker-arm 

>From a7930378450e1e75fe543c682d4ce31382c099fc Mon Sep 17 00:00:00 2001
From: dlee992 <lidanuaa at gmail.com>
Date: Thu, 6 Feb 2025 10:48:49 -0600
Subject: [PATCH] add NodeMap[V] for DAGBuilder cache

---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4e1ce6af3abc846..2c175ff621bea04 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1893,8 +1893,9 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
 
     if (VT == MVT::aarch64svcount) {
       assert(C->isNullValue() && "Can only zero this target type!");
-      return DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT,
-                         DAG.getConstant(0, getCurSDLoc(), MVT::nxv16i1));
+      return NodeMap[V] =
+                 DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT,
+                             DAG.getConstant(0, getCurSDLoc(), MVT::nxv16i1));
     }
 
     if (VT.isRISCVVectorTuple()) {