[llvm] [RISCV] Reduce the LMUL for a vrgather operation if legal (PR #125768)

[Philip Reames via llvm-commits]

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@@ -525,29 +525,25 @@ define void @vnsrl_0_i32_single_src_m8(ptr %in, ptr %out) {
 ; V-NEXT:    li a2, 64
 ; V-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
 ; V-NEXT:    vle32.v v8, (a0)
-; V-NEXT:    lui a0, 341
-; V-NEXT:    addiw a0, a0, 1365
-; V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; V-NEXT:    vmv.s.x v16, a0
+; V-NEXT:    vsetivli zero, 16, e32, m2, ta, ma
+; V-NEXT:    vnsrl.wi v16, v8, 0
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preames wrote:

I don't really see any value in duplicating given the undef tail is the canonical form for a single source deinterleave.  If it's not an undef tail, it can be a deinterleave by definition.  In real code, there'd probably be an extract subvector following it, not a full width store.  

https://github.com/llvm/llvm-project/pull/125768