[llvm] [IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (PR #124825)

Thu Feb 6 00:03:20 PST 2025

mikaelholmen wrote:

Many bot failures above. I can just add what I've seen manually:
If I build with EXPENSIVE_CHECKS I see that test/CodeGen/RISCV/rvv/vector-interleave.ll fails like
```
# After Post-RA pseudo instruction expansion pass
# Machine code for function vector_interleave_nxv80i1_nxv16i1: NoPHIs, TracksLiveness, NoVRegs, TiedOpsRewritten, TracksDebugUserValues
Frame Objects:
  fi#0: id=2 size=40, align=8, at location [SP-40]
  fi#1: id=2 size=40, align=8, at location [SP-80]
  fi#2: size=4, align=4, at location [SP-16]
Function Live Ins: $v0, $v8, $v9, $v10, $v11

bb.0 (%ir-block.0):
  liveins: $v0, $v8, $v9, $v10, $v11
  $x2 = frame-setup ADDI $x2, -16
  frame-setup CFI_INSTRUCTION def_cfa_offset 16
  $x10 = frame-setup PseudoReadVLENB
  $x11 = frame-setup ADDI $x0, 10
  $x10 = frame-setup MUL killed $x10, killed $x11
  $x2 = frame-setup SUB $x2, killed $x10
  frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x0a, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
  dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193, implicit-def $vl, implicit-def $vtype
  renamable $v12m2 = PseudoVMV_V_I_M2 undef renamable $v12m2(tied-def 0), 0, -1, 3, 0, implicit $vl, implicit $vtype
  renamable $x14 = ADDI $x2, 16
  $x10 = PseudoReadVLENB
  $x11 = SLLI $x10, 2
  $x10 = ADD killed $x11, killed $x10
  $x10 = ADD $x2, killed $x10
  renamable $x10 = ADDI killed $x10, 16
  renamable $x11 = PseudoReadVLENB
  renamable $v14m2 = PseudoVMERGE_VIM_M2 undef renamable $v14m2(tied-def 0), renamable $v12m2, 1, $v0, -1, 3, implicit $vl, implicit $vtype
  $v0 = VMV1R_V killed $v8, implicit $vtype, implicit $vtype
  renamable $v18m2 = PseudoVMERGE_VIM_M2 undef renamable $v18m2(tied-def 0), renamable $v12m2, 1, $v0, -1, 3, implicit $vl, implicit $vtype
  renamable $x12 = ADD renamable $x14, renamable $x11
  renamable $x13 = SRLI renamable $x11, 2
  $v20m2 = VMV2R_V $v14m2, implicit $vtype
  $v22m2 = VMV2R_V $v16m2, implicit $vtype
  $v24 = VMV1R_V $v18, implicit $vtype, implicit $vtype
  $v0 = VMV1R_V killed $v9, implicit $vtype, implicit $vtype
  renamable $v16m2 = PseudoVMERGE_VIM_M2 undef renamable $v16m2(tied-def 0), renamable $v12m2, 1, $v0, -1, 3, implicit $vl, implicit $vtype
  $v21 = VMV1R_V $v18, implicit $vtype, implicit $vtype
  $v0 = VMV1R_V killed $v10, implicit $vtype, implicit $vtype
  renamable $v8m2 = PseudoVMERGE_VIM_M2 undef renamable $v8m2(tied-def 0), renamable $v12m2, 1, $v0, -1, 3, implicit $vl, implicit $vtype
  $v22 = VMV1R_V $v16, implicit $vtype, implicit $vtype
  $v16 = VMV1R_V killed $v19, implicit $vtype, implicit $vtype
  renamable $x15 = ADD renamable $x12, renamable $x11
  $v23 = VMV1R_V $v8, implicit $vtype, implicit $vtype
  $v18 = VMV1R_V killed $v9, implicit $vtype, implicit $vtype
  $v0 = VMV1R_V killed $v11, implicit $vtype, implicit $vtype
  renamable $v24m2 = PseudoVMERGE_VIM_M2 undef renamable $v24m2(tied-def 0), killed renamable $v12m2, 1, $v0, -1, 3, implicit $vl, implicit $vtype
  dead renamable $x16 = PseudoVSETVLIX0 killed $x0, 192, implicit-def $vl, implicit-def $vtype
  PseudoVSSEG5E8_V_M1 renamable $v20_v21_v22_v23_v24, renamable $x14, -1, 3, implicit $vl, implicit $vtype :: (store unknown-size into %stack.1, align 8)
  $v19 = VMV1R_V killed $v25, implicit $vtype, implicit $vtype
  PseudoVSSEG5E8_V_M1 killed renamable $v15_v16_v17_v18_v19, renamable $x10, -1, 3, implicit $vl, implicit $vtype :: (store unknown-size into %stack.0, align 8)
  renamable $v8 = VL1RE8_V renamable $x15 :: (load (<vscale x 1 x s64>) from %stack.1)
  renamable $x15 = ADD killed renamable $x15, renamable $x11
  renamable $v10 = VL1RE8_V killed renamable $x14 :: (load (<vscale x 1 x s64>) from %stack.1)
  renamable $x14 = ADD renamable $x15, renamable $x11
  renamable $v12 = VL1RE8_V killed renamable $x14 :: (load (<vscale x 1 x s64>) from %stack.1)
  renamable $x14 = ADD renamable $x10, renamable $x11
  renamable $v14 = VL1RE8_V renamable $x14 :: (load (<vscale x 1 x s64>) from %stack.0)
  renamable $x14 = ADD killed renamable $x14, renamable $x11
  renamable $v9 = VL1RE8_V killed renamable $x15 :: (load (<vscale x 1 x s64>) from %stack.1)
  renamable $x15 = ADD renamable $x14, renamable $x11
  renamable $v16 = VL1RE8_V renamable $x15 :: (load (<vscale x 1 x s64>) from %stack.0)
  renamable $x15 = ADD killed renamable $x15, renamable $x11
  renamable $x11 = SRLI killed renamable $x11, 1
  renamable $v11 = VL1RE8_V killed renamable $x12 :: (load (<vscale x 1 x s64>) from %stack.1)
  renamable $x12 = ADD renamable $x13, renamable $x13
  renamable $v15 = VL1RE8_V killed renamable $x14 :: (load (<vscale x 1 x s64>) from %stack.0)
  renamable $x14 = ADD renamable $x11, renamable $x11
  renamable $v13 = VL1RE8_V killed renamable $x10 :: (load (<vscale x 1 x s64>) from %stack.0)
  renamable $v17 = VL1RE8_V killed renamable $x15 :: (load (<vscale x 1 x s64>) from %stack.0)
  dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193, implicit-def $vl, implicit-def $vtype
  early-clobber renamable $v18 = PseudoVMSNE_VI_M2 killed renamable $v8m2, 0, -1, 3, implicit $vl, implicit $vtype
  early-clobber renamable $v0 = PseudoVMSNE_VI_M2 killed renamable $v10m2, 0, -1, 3, implicit $vl, implicit $vtype
  early-clobber renamable $v8 = PseudoVMSNE_VI_M2 killed renamable $v14m2, 0, -1, 3, implicit $vl, implicit $vtype
  early-clobber renamable $v9 = PseudoVMSNE_VI_M2 killed renamable $v12m2, 0, -1, 3, implicit $vl, implicit $vtype
  dead $x0 = PseudoVSETVLI killed renamable $x12, 199, implicit-def $vl, implicit-def $vtype
  early-clobber renamable $v0 = PseudoVSLIDEUP_VX_MF2 killed renamable $v0(tied-def 0), killed renamable $v18, renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype
  early-clobber renamable $v9 = PseudoVSLIDEUP_VX_MF2 killed renamable $v9(tied-def 0), killed renamable $v8, killed renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype
  dead $x0 = PseudoVSETVLI killed renamable $x14, 192, implicit-def $vl, implicit-def $vtype
  early-clobber renamable $v0 = PseudoVSLIDEUP_VX_M1 killed renamable $v0(tied-def 0), killed renamable $v9, killed renamable $x11, $noreg, 3, 1, implicit $vl, implicit $vtype
  dead renamable $x10 = PseudoVSETVLIX0 killed $x0, 193, implicit-def $vl, implicit-def $vtype
  early-clobber renamable $v8 = PseudoVMSNE_VI_M2 killed renamable $v16m2, 0, -1, 3, implicit $vl, implicit $vtype
  $x10 = frame-destroy PseudoReadVLENB
  $x11 = frame-destroy ADDI $x0, 10
  $x10 = frame-destroy MUL killed $x10, killed $x11
  $x2 = frame-destroy ADD $x2, killed $x10
  frame-destroy CFI_INSTRUCTION def_cfa $x2, 16
  $x2 = frame-destroy ADDI $x2, 16
  frame-destroy CFI_INSTRUCTION def_cfa_offset 0
  PseudoRET implicit $v0, implicit $v8

# End machine code for function vector_interleave_nxv80i1_nxv16i1.

*** Bad machine code: Using an undefined physical register ***
- function:    vector_interleave_nxv80i1_nxv16i1
- basic block: %bb.0  (0x56042f143608)
- instruction: $v22m2 = VMV2R_V $v16m2, implicit $vtype
- operand 1:   $v16m2
LLVM ERROR: Found 1 machine code errors.
```

https://github.com/llvm/llvm-project/pull/124825