[llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #126001)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 5 20:55:35 PST 2025
https://github.com/kazutakahirata created https://github.com/llvm/llvm-project/pull/126001
None
>From 41b30e8561e4707a9046eea46b305be97e2bc03c Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Wed, 5 Feb 2025 09:25:52 -0800
Subject: [PATCH] [AMDGPU] Avoid repeated hash lookups (NFC)
---
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
index 904321a344db115..708acc9f88445a2 100644
--- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -2174,12 +2174,13 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
// Step1: Find the base-registers and a 64bit constant offset.
MachineOperand &Base = *TII->getNamedOperand(MI, AMDGPU::OpName::vaddr);
+ auto [It, Inserted] = Visited.try_emplace(&MI);
MemAddress MAddr;
- if (!Visited.contains(&MI)) {
+ if (Inserted) {
processBaseWithConstOffset(Base, MAddr);
- Visited[&MI] = MAddr;
+ It->second = MAddr;
} else
- MAddr = Visited[&MI];
+ MAddr = It->second;
if (MAddr.Offset == 0) {
LLVM_DEBUG(dbgs() << " Failed to extract constant-offset or there are no"
@@ -2239,11 +2240,12 @@ bool SILoadStoreOptimizer::promoteConstantOffsetToImm(
const MachineOperand &BaseNext =
*TII->getNamedOperand(MINext, AMDGPU::OpName::vaddr);
MemAddress MAddrNext;
- if (!Visited.contains(&MINext)) {
+ auto [It, Inserted] = Visited.try_emplace(&MINext);
+ if (Inserted) {
processBaseWithConstOffset(BaseNext, MAddrNext);
- Visited[&MINext] = MAddrNext;
+ It->second = MAddrNext;
} else
- MAddrNext = Visited[&MINext];
+ MAddrNext = It->second;
if (MAddrNext.Base.LoReg != MAddr.Base.LoReg ||
MAddrNext.Base.HiReg != MAddr.Base.HiReg ||
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