[llvm] [RISCV] Reduce the LMUL for a vrgather operation if legal (PR #125768)

[Luke Lau via llvm-commits]

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@@ -525,29 +525,25 @@ define void @vnsrl_0_i32_single_src_m8(ptr %in, ptr %out) {
 ; V-NEXT:    li a2, 64
 ; V-NEXT:    vsetvli zero, a2, e32, m8, ta, ma
 ; V-NEXT:    vle32.v v8, (a0)
-; V-NEXT:    lui a0, 341
-; V-NEXT:    addiw a0, a0, 1365
-; V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; V-NEXT:    vmv.s.x v16, a0
+; V-NEXT:    vsetivli zero, 16, e32, m2, ta, ma
+; V-NEXT:    vnsrl.wi v16, v8, 0
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lukel97 wrote:

This is a nice win/way to workaround the previous limitation of m8. 

Should we duplicate the test without the undef indices though so we're still testing the negative case

https://github.com/llvm/llvm-project/pull/125768