[llvm] Reduce shl64 to shl32 if shift range is [63-32] (PR #125574)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,67 @@
+;; Test reduction of:
+;;
+;;   DST = shl i64 X, Y
+;;
+;; where Y is in the range [63-32] to:
+;;
+;;   DST = [0, shl i32 X, (Y - 32)]
+
+; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
+
+; FIXME: This case should be reduced, but SelectionDAG::computeKnownBits() cannot
+;        determine the minimum from metadata in this case.  Match current results
+;        for now.
+define i64 @shl_metadata(i64 noundef %arg0, ptr %arg1.ptr) {
+  %shift.amt = load i64, ptr %arg1.ptr, !range !0
+  %shl = shl i64 %arg0, %shift.amt
+  ret i64 %shl
+
+; CHECK: .globl  shl_metadata
+; CHECK: v_lshl_b64 v[0:1], v[0:1], v2
+}
+
+!0 = !{i64 32, i64 64}
+
+; This case is reduced because computeKnownBits() can calculates a minimum of 32
+; based on the OR with 32.
+define i64 @shl_or32(i64 noundef %arg0, ptr %arg1.ptr) {
+  %shift.amt = load i64, ptr %arg1.ptr
+  %or = or i64 %shift.amt, 32
+  %shl = shl i64 %arg0, %or
+  ret i64 %shl
+
+; CHECK: .globl  shl_or32
+; CHECK: v_or_b32_e32 v1, 32, v1
+; CHECK: v_subrev_i32_e32 v1, vcc, 32, v1
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arsenm wrote:

I forgot about this additional sub. I see what you mean about the cost. I thought 64 bit shifts were always quarter rate, so replacing with 2 full rate instructions would be a win. Should double check how many cycles this is 

https://github.com/llvm/llvm-project/pull/125574