[llvm] [SelectionDAG] Add PARTIAL_REDUCE_U/SMLA ISD Nodes (PR #125207)

[Paul Walker via llvm-commits]

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@@ -503,6 +503,8 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
   case ISD::VECREDUCE_FMIN:
   case ISD::VECREDUCE_FMAXIMUM:
   case ISD::VECREDUCE_FMINIMUM:
+  case ISD::PARTIAL_REDUCE_UMLA:
+  case ISD::PARTIAL_REDUCE_SMLA:
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paulwalker-arm wrote:

If my previous comment (on LegalizeDAG.cpp) is correct then for consistency you'd add these entries to the block that reads `Node->getValueType(0)`.

https://github.com/llvm/llvm-project/pull/125207