[llvm] [RISCV] Reduce the LMUL for a vrgather operation if legal (PR #125768)

[Philip Reames via llvm-commits]

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@@ -874,27 +874,30 @@ define <16 x i8> @reverse_v16i8_2(<8 x i8> %a, <8 x i8> %b) {
 define <32 x i8> @reverse_v32i8_2(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: reverse_v32i8_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vmv1r.v v10, v9
 ; CHECK-NEXT:    csrr a0, vlenb
-; CHECK-NEXT:    vid.v v12
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vid.v v10
 ; CHECK-NEXT:    addi a1, a0, -1
-; CHECK-NEXT:    vrsub.vx v12, v12, a1
+; CHECK-NEXT:    vrsub.vx v10, v10, a1
 ; CHECK-NEXT:    lui a1, 16
 ; CHECK-NEXT:    addi a1, a1, -1
 ; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vrgatherei16.vv v15, v8, v12
-; CHECK-NEXT:    vrgatherei16.vv v14, v9, v12
+; CHECK-NEXT:    vrgatherei16.vv v15, v8, v10
+; CHECK-NEXT:    vrgatherei16.vv v14, v12, v10
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preames wrote:

I wasn't, and had a moment of panic as this was also in the other change I landed last night, but this is correct.

We're lowering a shuffle <undef, undef, undef, undef, 3, 2,1,0> here.  This is recognized as a reverse, but the high lanes of the source are undefined and undemanded.  This has been true the whole time, but the perturbation of register allocation in this patch happens to cause them to pick a different register.

We could arguably do a better lowering here - e.g. reverse m1 then slide - but doing that will only save a linear number of m1 vrgathers at best.  



https://github.com/llvm/llvm-project/pull/125768