[llvm] [RISCV] Match widening fp instructions with same fpext used in multiple operands (PR #125803)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 5 04:59:39 PST 2025
https://github.com/llvm updated https://github.com/llvm/llvm-project/pull/125803
>From 9f9ce6a69c12e6e6f685fb7092d297257e5e634e Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 5 Feb 2025 13:11:00 +0800
Subject: [PATCH 1/4] Precommit tests
---
llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll | 13 +++++++++
llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll | 29 +++++++++++++++++++
llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll | 13 +++++++++
llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll | 13 +++++++++
4 files changed, 68 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
index 68014ff4206f8ad..edc3480146c6f59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
@@ -323,3 +323,16 @@ define <vscale x 8 x double> @vfwadd_wf_nxv8f64_2(<vscale x 8 x double> %va, flo
%vd = fadd <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vd
}
+
+define <vscale x 1 x double> @vfwadd_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
+; CHECK-LABEL: vfwadd_vv_nxv1f64_same_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfadd.vv v8, v9, v9
+; CHECK-NEXT: ret
+ %vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %vc = fadd <vscale x 1 x double> %vb, %vb
+ ret <vscale x 1 x double> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
index f69b2346226ee99..c0661b3a649da0b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
@@ -1764,3 +1764,32 @@ define <vscale x 8 x double> @vfwnmsac_fv_nxv8f64(<vscale x 8 x double> %va, <vs
%vg = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vd, <vscale x 8 x double> %vf, <vscale x 8 x double> %va)
ret <vscale x 8 x double> %vg
}
+
+define <vscale x 1 x double> @vfwma_vv_nxv1f64_same_op(<vscale x 1 x float> %va, <vscale x 1 x double> %vb) {
+; CHECK-LABEL: vfwma_vv_nxv1f64_same_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmadd.vv v10, v10, v9
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %vd = call <vscale x 1 x double> @llvm.fma(<vscale x 1 x double> %vc, <vscale x 1 x double> %vc, <vscale x 1 x double> %vb)
+ ret <vscale x 1 x double> %vd
+}
+
+define <vscale x 1 x double> @vfwmsac_vv_nxv1f64_same_op(<vscale x 1 x float> %va, <vscale x 1 x double> %vb) {
+; CHECK-LABEL: vfwmsac_vv_nxv1f64_same_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v10, v8
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmsub.vv v10, v10, v9
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %vd = fneg <vscale x 1 x double> %vb
+ %ve = call <vscale x 1 x double> @llvm.fma(<vscale x 1 x double> %vc, <vscale x 1 x double> %vc, <vscale x 1 x double> %vd)
+ ret <vscale x 1 x double> %ve
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
index f00ff4b6d2cec2a..e831e99040fa1a8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
@@ -175,3 +175,16 @@ define <vscale x 8 x double> @vfwmul_vf_nxv8f64_2(<vscale x 8 x float> %va, floa
%ve = fmul <vscale x 8 x double> %vc, %splat
ret <vscale x 8 x double> %ve
}
+
+define <vscale x 1 x double> @vfwmul_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
+; CHECK-LABEL: vfwmul_vv_nxv1f64_same_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfmul.vv v8, v9, v9
+; CHECK-NEXT: ret
+ %vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %vc = fmul <vscale x 1 x double> %vb, %vb
+ ret <vscale x 1 x double> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
index b9f66d5d30825d4..3c2c12eacc91058 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
@@ -323,3 +323,16 @@ define <vscale x 8 x double> @vfwsub_wf_nxv8f64_2(<vscale x 8 x double> %va, flo
%vd = fsub <vscale x 8 x double> %va, %splat
ret <vscale x 8 x double> %vd
}
+
+define <vscale x 1 x double> @vfwsub_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
+; CHECK-LABEL: vfwsub_vv_nxv1f64_same_op:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; CHECK-NEXT: vfwcvt.f.f.v v9, v8
+; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-NEXT: vfsub.vv v8, v9, v9
+; CHECK-NEXT: ret
+ %vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
+ %vc = fsub <vscale x 1 x double> %vb, %vb
+ ret <vscale x 1 x double> %vc
+}
>From a0005edcd8ad00d9dbe0149f930723e5f938c86c Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 5 Feb 2025 13:22:03 +0800
Subject: [PATCH 2/4] [RISCV] Match widening fp instructions with same fpext
used in multiple operands
Because the fpext has a single use constraint on it we can't match cases where it's used for both operands.
Introduce a new PatFrag that allows multiple uses on a single user and use it for the binary patterns, and some ternary patterns.
(For some of the ternary patterns there is a fneg that counts as a separate user, we still need to handle these)
---
.../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 26 +++++++++----------
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 5 ++++
llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll | 5 ++--
llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll | 12 +++------
llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll | 5 ++--
llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll | 5 ++--
6 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 8f77b2ce34d1f19..72f91f71e78537e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -536,19 +536,19 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
+ (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
+ (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -571,10 +571,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
+ (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW)
@@ -584,10 +584,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// RISCVInsertReadWriteCSR
FRM_DYN,
vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
+ (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector (SplatFPOp (vti.Scalar vti.ScalarRegClass:$rs1))),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
@@ -669,10 +669,10 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
!if(!eq(vti.Scalar, bf16),
[HasStdExtZvfbfwma],
[])) in {
- def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
+ def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuse
+ (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector wti.RegClass:$rd)),
@@ -749,11 +749,11 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuse
+ def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ (riscv_fpextend_vl_oneuser (vti.Vector vti.RegClass:$rs2),
+ (vti.Mask true_mask), (XLenVT srcvalue)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 333ae52534681a1..0e6f807ae26af5b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -554,6 +554,11 @@ def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),
return N->hasOneUse();
}]>;
+def riscv_fpextend_vl_oneuser : PatFrag<(ops node:$A, node:$B, node:$C),
+ (riscv_fpextend_vl node:$A, node:$B, node:$C), [{
+ return !N->use_empty() && all_equal(N->users());
+}]>;
+
def riscv_vfmadd_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
node:$E),
(riscv_vfmadd_vl node:$A, node:$B,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
index edc3480146c6f59..f7d287a088cc3ed 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll
@@ -328,9 +328,8 @@ define <vscale x 1 x double> @vfwadd_vv_nxv1f64_same_op(<vscale x 1 x float> %va
; CHECK-LABEL: vfwadd_vv_nxv1f64_same_op:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfadd.vv v8, v9, v9
+; CHECK-NEXT: vfwadd.vv v9, v8, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vc = fadd <vscale x 1 x double> %vb, %vb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
index c0661b3a649da0b..63113b878098943 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll
@@ -1769,10 +1769,8 @@ define <vscale x 1 x double> @vfwma_vv_nxv1f64_same_op(<vscale x 1 x float> %va,
; CHECK-LABEL: vfwma_vv_nxv1f64_same_op:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmadd.vv v10, v10, v9
-; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vfwmacc.vv v9, v8, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = call <vscale x 1 x double> @llvm.fma(<vscale x 1 x double> %vc, <vscale x 1 x double> %vc, <vscale x 1 x double> %vb)
@@ -1783,10 +1781,8 @@ define <vscale x 1 x double> @vfwmsac_vv_nxv1f64_same_op(<vscale x 1 x float> %v
; CHECK-LABEL: vfwmsac_vv_nxv1f64_same_op:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v10, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmsub.vv v10, v10, v9
-; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: vfwmsac.vv v9, v8, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fneg <vscale x 1 x double> %vb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
index e831e99040fa1a8..8cc8c5cffca6b27 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul-sdnode.ll
@@ -180,9 +180,8 @@ define <vscale x 1 x double> @vfwmul_vv_nxv1f64_same_op(<vscale x 1 x float> %va
; CHECK-LABEL: vfwmul_vv_nxv1f64_same_op:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfmul.vv v8, v9, v9
+; CHECK-NEXT: vfwmul.vv v9, v8, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vc = fmul <vscale x 1 x double> %vb, %vb
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
index 3c2c12eacc91058..d0cb64d98666187 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll
@@ -328,9 +328,8 @@ define <vscale x 1 x double> @vfwsub_vv_nxv1f64_same_op(<vscale x 1 x float> %va
; CHECK-LABEL: vfwsub_vv_nxv1f64_same_op:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vfwcvt.f.f.v v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT: vfsub.vv v8, v9, v9
+; CHECK-NEXT: vfwsub.vv v9, v8, v8
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vc = fsub <vscale x 1 x double> %vb, %vb
>From 468517fb3a9aec37b7f9d16e2fa763f9483d5c60 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 5 Feb 2025 17:31:33 +0800
Subject: [PATCH 3/4] Rename to sameuser
---
.../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 26 +++++++++----------
.../Target/RISCV/RISCVInstrInfoVVLPatterns.td | 4 +--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 72f91f71e78537e..c588e047c2ac8fa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -536,19 +536,19 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuser
+ (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuser
+ (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -571,10 +571,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuser
+ (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_E"#vti.SEW)
@@ -584,10 +584,10 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// RISCVInsertReadWriteCSR
FRM_DYN,
vti.AVL, vti.Log2SEW, TA_MA)>;
- def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuser
+ def : Pat<(op (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuser
+ (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector (SplatFPOp (vti.Scalar vti.ScalarRegClass:$rs1))),
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_E"#vti.SEW)
@@ -669,10 +669,10 @@ multiclass VPatWidenFPMulAccSDNode_VV_VF_RM<string instruction_name,
!if(!eq(vti.Scalar, bf16),
[HasStdExtZvfbfwma],
[])) in {
- def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuser
+ def : Pat<(fma (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (wti.Vector (riscv_fpextend_vl_oneuser
+ (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector wti.RegClass:$rd)),
@@ -749,11 +749,11 @@ multiclass VPatWidenFPMulSacSDNode_VV_VF_RM<string instruction_name> {
defvar suffix = vti.LMul.MX # "_E" # vti.SEW;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in {
- def : Pat<(fma (wti.Vector (riscv_fpextend_vl_oneuser
+ def : Pat<(fma (wti.Vector (riscv_fpextend_vl_sameuser
(vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue))),
- (riscv_fpextend_vl_oneuser (vti.Vector vti.RegClass:$rs2),
- (vti.Mask true_mask), (XLenVT srcvalue)),
+ (riscv_fpextend_vl_sameuser (vti.Vector vti.RegClass:$rs2),
+ (vti.Mask true_mask), (XLenVT srcvalue)),
(fneg wti.RegClass:$rd)),
(!cast<Instruction>(instruction_name#"_VV_"#suffix)
wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 0e6f807ae26af5b..f63c1560f625382 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -554,8 +554,8 @@ def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C),
return N->hasOneUse();
}]>;
-def riscv_fpextend_vl_oneuser : PatFrag<(ops node:$A, node:$B, node:$C),
- (riscv_fpextend_vl node:$A, node:$B, node:$C), [{
+def riscv_fpextend_vl_sameuser : PatFrag<(ops node:$A, node:$B, node:$C),
+ (riscv_fpextend_vl node:$A, node:$B, node:$C), [{
return !N->use_empty() && all_equal(N->users());
}]>;
>From 8ef796612a7ed4a4bcab75e7a4ab3f3349104ab5 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 5 Feb 2025 19:32:58 +0800
Subject: [PATCH 4/4] wake up github
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