[llvm] [AMDGPU] Mark AGPR tuple implicit in the first instr of AGPR spills. (PR #115285)

[Vikash Gupta via llvm-commits]

vg0204 wrote:

@arsenm addressing your https://github.com/llvm/llvm-project/pull/115285#discussion_r1841007270, cannot we have just additional explicit operand(maybe uint64(MO_Immediate) capable of representing LaneMaskbits for RegUnits in physRegisters) in those Machine instruction which needs breaking of tupleRegs such as COPY or SPILL. Wouldn't be better than MO_Register to supposedly have hold mask that would make MO bigger despite the fact the laneMask is used very oftenly as discussed here.

CC : @jayfoad , @cdevadas , @jrbyrnes 

https://github.com/llvm/llvm-project/pull/115285