[llvm] [MachineScheduler][RISCV] Release the pending queue base on condition (PR #125468)

[Pengcheng Wang via llvm-commits]

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@@ -1190,6 +1190,23 @@ class TargetRegisterInfo : public MCRegisterInfo {
     return false;
   }
 
+  /// Based on the target and current register pressure information from the
+  /// Scheduler, determine whether to release the node in the pending queue
+  virtual bool
+  needReleasePendingQueue(MachineFunction &MF,
+                          ArrayRef<unsigned> MaxSetPressure) const {
+    return false;
+  }
+
+  /// For each SUnit, determine whether to release it
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wangpc-pp wrote:

The format is wrong here.

https://github.com/llvm/llvm-project/pull/125468