[llvm] [MachineScheduler][RISCV] Release the pending queue base on condition (PR #125468)

[Pengcheng Wang via llvm-commits]

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@@ -954,3 +954,36 @@ bool RISCVRegisterInfo::getRegAllocationHints(
 
   return BaseImplRetVal;
 }
+
+bool RISCVRegisterInfo::needReleasePendingQueue(
+    MachineFunction &MF, ArrayRef<unsigned> MaxSetPressure) const {
+  for (unsigned Idx = 0; Idx < MaxSetPressure.size(); Idx++) {
+    // Consider only the RVV Register, as RVV spilling/reloading has higher
+    // potential costs than hazards.
+    if (!StringRef(getRegPressureSetName(Idx)).starts_with("VM") &&
+        !StringRef(getRegPressureSetName(Idx)).starts_with("VRM8NoV0"))
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wangpc-pp wrote:

The name of reg pressure sets are easily changed when adding new register classes, I suggest we just add a static helper to list/compare the vector reg pressure sets directly.

https://github.com/llvm/llvm-project/pull/125468