[llvm] [RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (PR #125795)

[Craig Topper via llvm-commits]

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@@ -57,6 +57,20 @@ class RISCVInstructionSelector : public InstructionSelector {
   const TargetRegisterClass *
   getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB) const;
 
+  static constexpr unsigned MaxRecursionDepth = 6;
+
+  bool hasAllNBitUsers(const MachineInstr &MI, unsigned Bits,
+                       const unsigned Depth = 0) const;
+  bool hasAllBUsers(const MachineInstr &MI) const {
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topperc wrote:

This has no callers and may give a warning in some builds.

https://github.com/llvm/llvm-project/pull/125795