[llvm] [RISCV] Porting hasAllNBitUsers to RISCV GISel for instruction select (PR #125795)

[Michael Maitland via llvm-commits]

================
@@ -184,6 +198,79 @@ RISCVInstructionSelector::RISCVInstructionSelector(
 {
 }
 
+// Mimics optimizations in ISel and RISCVOptWInst Pass
+bool RISCVInstructionSelector::hasAllNBitUsers(const MachineInstr &MI,
+                                               unsigned Bits,
+                                               const unsigned Depth) const {
+
+  assert((MI.getOpcode() == TargetOpcode::G_ADD ||
+          MI.getOpcode() == TargetOpcode::G_SUB ||
+          MI.getOpcode() == TargetOpcode::G_MUL ||
+          MI.getOpcode() == TargetOpcode::G_SHL ||
+          MI.getOpcode() == TargetOpcode::G_LSHR ||
+          MI.getOpcode() == TargetOpcode::G_AND ||
+          MI.getOpcode() == TargetOpcode::G_OR ||
+          MI.getOpcode() == TargetOpcode::G_XOR ||
+          MI.getOpcode() == TargetOpcode::G_SEXT_INREG || Depth != 0) &&
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michaelmaitland wrote:

RISCVDAGToDAGISel::hasAllNBitUsers has isa<ConstantSDNode>(Node) as part of this check. Any reason why we don't include G_CONSTANT here?

https://github.com/llvm/llvm-project/pull/125795