[llvm] SimplifyIndVar: teach widenLoopCompare about samesign (PR #125764)

[Nikita Popov via llvm-commits]

https://github.com/nikic commented:

Proof: https://alive2.llvm.org/ce/z/NVXaeo

I think something the tests don't cover is that the RHS is sign extended rather than zero extended. (They use constant 1 where it makes no difference.)

https://github.com/llvm/llvm-project/pull/125764