[llvm] [RISCV] Reduce the LMUL for a vrgather operation if legal (PR #125768)

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git-clang-format --diff ada8adfc2dd0ceaccb0c88565fe343864c5096ce f2c0c9f195510b956da7ad716c14e8c589fe0d60 --extensions cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a6cca57943..535b94c7d2 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5628,7 +5628,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
       for (auto [I, M] : enumerate(Mask)) {
         if (M == -1)
           continue;
-        MaxIdx = std::max(std::max((unsigned)I,(unsigned)M), MaxIdx);
+        MaxIdx = std::max(std::max((unsigned)I, (unsigned)M), MaxIdx);
       }
       unsigned NewNumElts = NumElts;
       while (MaxIdx < NewNumElts / 2 && NewNumElts != MinVLMAX)
@@ -5639,8 +5639,8 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
         V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewVT, V1, ZeroIdx);
         SDValue Res = DAG.getVectorShuffle(NewVT, DL, V1, DAG.getUNDEF(NewVT),
                                            Mask.take_front(NewNumElts));
-        return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
-                           Res, ZeroIdx);
+        return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Res,
+                           ZeroIdx);
       }
     }
 

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https://github.com/llvm/llvm-project/pull/125768