[llvm] [msan][NFCI] Add tests for sum long across vector (PR #125761)

[Thurston Dang via llvm-commits]

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@@ -0,0 +1,64 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -passes=msan -S | FileCheck %s
+;
+; Forked from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll
+;
+; Currently handled (suboptimally) by handleUnknownInstruction:
+; - llvm.aarch64.neon.saddlv
+; - llvm.aarch64.neon.uaddlv
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-android9001"
+
+define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone #0 {
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thurstond wrote:

This is cloned from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll so I don't know for sure, but my guess is:
- they adopted a convention of "arm64-v" as the filename, to denote vector instructions
- internally, they use the filename for the test names (and append "_s" or "_u" for signed/unsigned)

Note that 

https://github.com/llvm/llvm-project/pull/125761