[llvm] 9a9b70a - [PhaseOrdering][X86] Add test coverage for #58139
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 4 03:07:19 PST 2025
Author: Simon Pilgrim
Date: 2025-02-04T11:06:18Z
New Revision: 9a9b70aa87632408298ea02c28a605c02a383c3a
URL: https://github.com/llvm/llvm-project/commit/9a9b70aa87632408298ea02c28a605c02a383c3a
DIFF: https://github.com/llvm/llvm-project/commit/9a9b70aa87632408298ea02c28a605c02a383c3a.diff
LOG: [PhaseOrdering][X86] Add test coverage for #58139
Added:
Modified:
llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
index 84eba813b179d5d..5794b497cf7023f 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
@@ -97,3 +97,30 @@ define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %
store float %add10, ptr %r3, align 4
ret void
}
+
+; PR58139
+define <2 x double> @_mm_complexmult_pd_naive(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @_mm_complexmult_pd_naive(
+; CHECK-NEXT: [[B1:%.*]] = extractelement <2 x double> [[B:%.*]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = fneg double [[B1]]
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[B]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP2]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[A]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP7:%.*]] = tail call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP6]], <2 x double> [[B]], <2 x double> [[TMP5]])
+; CHECK-NEXT: ret <2 x double> [[TMP7]]
+;
+ %a0 = extractelement <2 x double> %a, i32 0
+ %a1 = extractelement <2 x double> %a, i32 1
+ %b0 = extractelement <2 x double> %b, i32 0
+ %b1 = extractelement <2 x double> %b, i32 1
+ %mul10 = fmul double %a1, %b0
+ %mul11 = fmul double %a1, %b1
+ %neg11 = fneg double %mul11
+ %madd0 = call double @llvm.fmuladd.f64(double %a0, double %b0, double %neg11)
+ %madd1 = call double @llvm.fmuladd.f64(double %a0, double %b1, double %mul10)
+ %res0 = insertelement <2 x double> poison, double %madd0, i32 0
+ %res1 = insertelement <2 x double> %res0, double %madd1, i32 1
+ ret <2 x double> %res1
+}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll b/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
index 870ae4ec20e4c67..053f9f3c1c2828b 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/addsub.ll
@@ -97,3 +97,30 @@ define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %
store float %add10, ptr %r3, align 4
ret void
}
+
+; PR58139
+define <2 x double> @_mm_complexmult_pd_naive(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @_mm_complexmult_pd_naive(
+; CHECK-NEXT: [[B1:%.*]] = extractelement <2 x double> [[B:%.*]], i64 1
+; CHECK-NEXT: [[TMP1:%.*]] = fneg double [[B1]]
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[B]], <2 x double> poison, <2 x i32> <i32 poison, i32 0>
+; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[TMP1]], i64 0
+; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP2]], [[TMP4]]
+; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[A]], <2 x double> poison, <2 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP7:%.*]] = tail call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP6]], <2 x double> [[B]], <2 x double> [[TMP5]])
+; CHECK-NEXT: ret <2 x double> [[TMP7]]
+;
+ %a0 = extractelement <2 x double> %a, i32 0
+ %a1 = extractelement <2 x double> %a, i32 1
+ %b0 = extractelement <2 x double> %b, i32 0
+ %b1 = extractelement <2 x double> %b, i32 1
+ %mul10 = fmul double %a1, %b0
+ %mul11 = fmul double %a1, %b1
+ %neg11 = fneg double %mul11
+ %madd0 = call double @llvm.fmuladd.f64(double %a0, double %b0, double %neg11)
+ %madd1 = call double @llvm.fmuladd.f64(double %a0, double %b1, double %mul10)
+ %res0 = insertelement <2 x double> undef, double %madd0, i32 0
+ %res1 = insertelement <2 x double> %res0, double %madd1, i32 1
+ ret <2 x double> %res1
+}
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