[llvm] [AMDGPU] Avoid repeated hash lookups (NFC) (PR #125632)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 3 21:32:55 PST 2025
https://github.com/kazutakahirata created https://github.com/llvm/llvm-project/pull/125632
None
>From 9895fb9863286e64d9da412d94534bad9fce5df9 Mon Sep 17 00:00:00 2001
From: Kazu Hirata <kazu at google.com>
Date: Mon, 3 Feb 2025 16:39:17 -0800
Subject: [PATCH] [AMDGPU] Avoid repeated hash lookups (NFC)
---
llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
index a20319ea4f9d35..ac11526da0919c 100644
--- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
+++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
@@ -287,10 +287,10 @@ bool R600VectorRegMerger::tryMergeUsingFreeSlot(RegSeqInfo &RSI,
RegSeqInfo &CompatibleRSI,
std::vector<std::pair<unsigned, unsigned>> &RemapChan) {
unsigned NeededUndefs = 4 - RSI.UndefReg.size();
- if (PreviousRegSeqByUndefCount[NeededUndefs].empty())
- return false;
std::vector<MachineInstr *> &MIs =
PreviousRegSeqByUndefCount[NeededUndefs];
+ if (MIs.empty())
+ return false;
CompatibleRSI = PreviousRegSeq[MIs.back()];
tryMergeVector(&CompatibleRSI, &RSI, RemapChan);
return true;
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