[llvm] [AArch64] Combine separate vector and scalar tablegen SDNode record for AArch64ISD::REV16. NFC (PR #125614)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/125614

It's not a good idea to have two different SDNode records with different SDTypeProfiles. SDTypeProfiles are used to remove some unneeded checks from the GenDAGISel.inc. Having different SDTypeProfiles can cause checks to be removed that can create ambiguous matches, but that did not happen in this case.

With this change the AArchGenDAGISel.inc is identical. The only change is AArch64GenGlobalISel.inc which now includes scalar patterns for G_REV16 due to them now being picks up by an SDNodeEquiv. GISel does not yet use G_REV16 for scalars so this is not a functional change.

>From cedcb9d26e9bdf3b4159105ee522cd78c1297544 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 3 Feb 2025 17:04:17 -0800
Subject: [PATCH] [AArch64] Combine separate vector and scalar tablegen SDNode
 record for AArch64ISD::REV16. NFC

It's not a good idea to have two different SDNode records with
different SDTypeProfiles. SDTypeProfiles are used to remove some
unneeded checks from the GenDAGISel.inc. Having different
SDTypeProfiles can cause checks to be removed that can create
ambiguous matches, but that did not happen in this case.

With this change the AArchGenDAGISel.inc is identical. The only change
is AArch64GenGlobalISel.inc which now includes scalar patterns for
G_REV16 due to them now being picks up by an SDNodeEquiv. GISel
does not yet use G_REV16 for scalars so this is not a functional change.
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.td | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 3c57ba414b2bf07..88a061e8f577dbb 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -817,9 +817,7 @@ def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
 
-def AArch64rev16_scalar : SDNode<"AArch64ISD::REV16", SDTIntUnaryOp>;
-
-def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
+def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDTIntUnaryOp>;
 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
@@ -3000,8 +2998,8 @@ def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
 def : Pat<(srl (bswap top16Zero:$Rn), (i64 16)), (REV16Wr GPR32:$Rn)>;
 def : Pat<(srl (bswap top32Zero:$Rn), (i64 32)), (REV32Xr GPR64:$Rn)>;
 
-def : Pat<(AArch64rev16_scalar GPR32:$Rn), (REV16Wr GPR32:$Rn)>;
-def : Pat<(AArch64rev16_scalar GPR64:$Rn), (REV16Xr GPR64:$Rn)>;
+def : Pat<(AArch64rev16 GPR32:$Rn), (REV16Wr GPR32:$Rn)>;
+def : Pat<(AArch64rev16 GPR64:$Rn), (REV16Xr GPR64:$Rn)>;
 
 def : Pat<(or (and (srl GPR64:$Rn, (i64 8)), (i64 0x00ff00ff00ff00ff)),
               (and (shl GPR64:$Rn, (i64 8)), (i64 0xff00ff00ff00ff00))),