[llvm] [AArch64][SelectionDAG] Add CodeGen support for scalar FEAT_CPA (PR #105669)

[David Green via llvm-commits]

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@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress",  SDTPtrLeaf, [],
 
 def add        : SDNode<"ISD::ADD"       , SDTIntBinOp   ,
                         [SDNPCommutative, SDNPAssociative]>;
-def ptradd     : SDNode<"ISD::ADD"       , SDTPtrAddOp, []>;
+def ptradd     : SDNode<"ISD::PTRADD"    , SDTPtrAddOp, []>;
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davemgreen wrote:

If you are redefining the meaning of this node then we should update the existing uses of it. I see only 1 in the AMDGPU backend, which is probably covered by add, but we should check it can be removed as the new meaning is different.

https://github.com/llvm/llvm-project/pull/105669