[llvm] [MISched] Small debug improvements (PR #125072)
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 3 02:36:39 PST 2025
https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/125072
>From 2e055fe07046c01aac74a1575786c612e39dfca8 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Thu, 30 Jan 2025 11:50:03 +0000
Subject: [PATCH 1/5] [MISched] Small debug improvements
Changes:
1. Fix inconsistencies in register pressure set printing. "Max Pressure"
printing is inconsistent with "Bottom Pressure" and "Top Pressure".
For the former, register class begins on the same line vs newline for
latter. Also for the former, the first register class is on the same
line, but subsequent register classes are newline separated. That's
removed so all are on the same line.
Before:
Max Pressure: FPR8=1
GPR32=14
Top Pressure:
GPR32=2
Bottom Pressure:
FPR8=7
GPR32=17
After:
Max Pressure: FPR8=1 GPR32=14
Top Pressure: GPR32=2
Bottom Pressure: FPR8=7 GPR32=17
2. After scheduling an instruction, don't print pressure diff if there
isn't one. Also s/UpdateRegP/UpdateRegPressure. E.g.,
Before:
UpdateRegP: SU(3) %0:gpr64common = ADDXrr %58:gpr64common, gpr64
to
UpdateRegP: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 390, 12
to GPR32 -1
After:
UpdateRegPressure: SU(4) %393:gpr64sp = ADDXri %58:gpr64common, 12
to GPR32 -1
3. Don't print excess pressure sets if there are none.
---
llvm/lib/CodeGen/MachineScheduler.cpp | 35 +++++++++++++++------------
llvm/lib/CodeGen/RegisterPressure.cpp | 7 ++----
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 393530f56cc27ee..e499dfa9822b960 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1293,9 +1293,9 @@ void ScheduleDAGMILive::initRegPressure() {
updatePressureDiffs(LiveUses);
}
- LLVM_DEBUG(dbgs() << "Top Pressure:\n";
+ LLVM_DEBUG(dbgs() << "Top Pressure: ";
dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
- dbgs() << "Bottom Pressure:\n";
+ dbgs() << "Bottom Pressure: ";
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI););
assert((BotRPTracker.getPos() == RegionEnd ||
@@ -1316,11 +1316,12 @@ void ScheduleDAGMILive::initRegPressure() {
RegionCriticalPSets.push_back(PressureChange(i));
}
}
- LLVM_DEBUG(dbgs() << "Excess PSets: ";
- for (const PressureChange &RCPS
- : RegionCriticalPSets) dbgs()
- << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
- dbgs() << "\n");
+ if (RegionCriticalPSets.size() > 0)
+ LLVM_DEBUG(dbgs() << "Excess PSets: ";
+ for (const PressureChange &RCPS
+ : RegionCriticalPSets) dbgs()
+ << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
+ dbgs() << "\n");
}
void ScheduleDAGMILive::
@@ -1374,10 +1375,11 @@ void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
PressureDiff &PDiff = getPressureDiff(&SU);
PDiff.addPressureChange(Reg, Decrement, &MRI);
- LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
- << printReg(Reg, TRI) << ':'
- << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
- dbgs() << " to "; PDiff.dump(*TRI););
+ if (llvm::any_of(PDiff, [](const PressureChange &Change) { return Change.isValid(); }))
+ LLVM_DEBUG(dbgs() << " UpdateRegPressure: SU(" << SU.NodeNum << ") "
+ << printReg(Reg, TRI) << ':'
+ << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
+ dbgs() << " to "; PDiff.dump(*TRI););
}
} else {
assert(P.LaneMask.any());
@@ -1409,9 +1411,10 @@ void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
if (LRQ.valueIn() == VNI) {
PressureDiff &PDiff = getPressureDiff(SU);
PDiff.addPressureChange(Reg, true, &MRI);
- LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
- << *SU->getInstr();
- dbgs() << " to "; PDiff.dump(*TRI););
+ if (llvm::any_of(PDiff, [](const PressureChange &Change) { return Change.isValid(); }))
+ LLVM_DEBUG(dbgs() << " UpdateRegPressure: SU(" << SU->NodeNum << ") "
+ << *SU->getInstr();
+ dbgs() << " to "; PDiff.dump(*TRI););
}
}
}
@@ -1671,7 +1674,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
TopRPTracker.advance(RegOpers);
assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
- LLVM_DEBUG(dbgs() << "Top Pressure:\n"; dumpRegSetPressure(
+ LLVM_DEBUG(dbgs() << "Top Pressure: "; dumpRegSetPressure(
TopRPTracker.getRegSetPressureAtPos(), TRI););
updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
@@ -1709,7 +1712,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
SmallVector<VRegMaskOrUnit, 8> LiveUses;
BotRPTracker.recede(RegOpers, &LiveUses);
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
- LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(
+ LLVM_DEBUG(dbgs() << "Bottom Pressure: "; dumpRegSetPressure(
BotRPTracker.getRegSetPressureAtPos(), TRI););
updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index e8e6db1e3b3bd14..ca51b670b46cce7 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -79,15 +79,12 @@ static void decreaseSetPressure(std::vector<unsigned> &CurrSetPressure,
LLVM_DUMP_METHOD
void llvm::dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
const TargetRegisterInfo *TRI) {
- bool Empty = true;
for (unsigned i = 0, e = SetPressure.size(); i < e; ++i) {
if (SetPressure[i] != 0) {
- dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n';
- Empty = false;
+ dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << ' ';
}
}
- if (Empty)
- dbgs() << "\n";
+ dbgs() << "\n";
}
LLVM_DUMP_METHOD
>From 62c7bb38dac1fdf775922fcd392e19509c23ebd7 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Thu, 30 Jan 2025 15:44:23 +0000
Subject: [PATCH 2/5] run clang-format
---
llvm/lib/CodeGen/MachineScheduler.cpp | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index e499dfa9822b960..8ea8d888e83fa50 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1375,10 +1375,13 @@ void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
PressureDiff &PDiff = getPressureDiff(&SU);
PDiff.addPressureChange(Reg, Decrement, &MRI);
- if (llvm::any_of(PDiff, [](const PressureChange &Change) { return Change.isValid(); }))
- LLVM_DEBUG(dbgs() << " UpdateRegPressure: SU(" << SU.NodeNum << ") "
- << printReg(Reg, TRI) << ':'
- << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
+ if (llvm::any_of(PDiff, [](const PressureChange &Change) {
+ return Change.isValid();
+ }))
+ LLVM_DEBUG(dbgs()
+ << " UpdateRegPressure: SU(" << SU.NodeNum << ") "
+ << printReg(Reg, TRI) << ':'
+ << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
dbgs() << " to "; PDiff.dump(*TRI););
}
} else {
@@ -1411,10 +1414,13 @@ void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
if (LRQ.valueIn() == VNI) {
PressureDiff &PDiff = getPressureDiff(SU);
PDiff.addPressureChange(Reg, true, &MRI);
- if (llvm::any_of(PDiff, [](const PressureChange &Change) { return Change.isValid(); }))
- LLVM_DEBUG(dbgs() << " UpdateRegPressure: SU(" << SU->NodeNum << ") "
- << *SU->getInstr();
- dbgs() << " to "; PDiff.dump(*TRI););
+ if (llvm::any_of(PDiff, [](const PressureChange &Change) {
+ return Change.isValid();
+ }))
+ LLVM_DEBUG(dbgs() << " UpdateRegPressure: SU(" << SU->NodeNum
+ << ") " << *SU->getInstr();
+ dbgs() << " to ";
+ PDiff.dump(*TRI););
}
}
}
>From 3c26a666608f4781c4a9c6801063cb7a37ba55bd Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Thu, 30 Jan 2025 16:09:00 +0000
Subject: [PATCH 3/5] manually format
upstream clang-format prefers this format whereas downstream prefers to
existing.
---
llvm/lib/CodeGen/MachineScheduler.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 8ea8d888e83fa50..8003c3270910ef6 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1318,8 +1318,7 @@ void ScheduleDAGMILive::initRegPressure() {
}
if (RegionCriticalPSets.size() > 0)
LLVM_DEBUG(dbgs() << "Excess PSets: ";
- for (const PressureChange &RCPS
- : RegionCriticalPSets) dbgs()
+ for (const PressureChange &RCPS : RegionCriticalPSets) dbgs()
<< TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
dbgs() << "\n");
}
>From 7373f88a31a0cb5d7aad8b69e57ba84bf887b71a Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Fri, 31 Jan 2025 13:36:16 +0000
Subject: [PATCH 4/5] add braces to fix botched clang-format
---
llvm/lib/CodeGen/MachineScheduler.cpp | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 8003c3270910ef6..1afc6774ae22113 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1317,10 +1317,12 @@ void ScheduleDAGMILive::initRegPressure() {
}
}
if (RegionCriticalPSets.size() > 0)
- LLVM_DEBUG(dbgs() << "Excess PSets: ";
- for (const PressureChange &RCPS : RegionCriticalPSets) dbgs()
- << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
- dbgs() << "\n");
+ LLVM_DEBUG({
+ dbgs() << "Excess PSets: ";
+ for (const PressureChange &RCPS : RegionCriticalPSets)
+ dbgs() << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
+ dbgs() << "\n";
+ });
}
void ScheduleDAGMILive::
>From 951cb970168c6d0c2c5d93eefd6a209de84ffda1 Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Mon, 3 Feb 2025 10:33:16 +0000
Subject: [PATCH 5/5] move if into LLVM_DEBUG
---
llvm/lib/CodeGen/MachineScheduler.cpp | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 1afc6774ae22113..5bbd3d10bf72e0a 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1316,13 +1316,14 @@ void ScheduleDAGMILive::initRegPressure() {
RegionCriticalPSets.push_back(PressureChange(i));
}
}
- if (RegionCriticalPSets.size() > 0)
- LLVM_DEBUG({
+ LLVM_DEBUG({
+ if (RegionCriticalPSets.size() > 0) {
dbgs() << "Excess PSets: ";
for (const PressureChange &RCPS : RegionCriticalPSets)
dbgs() << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
dbgs() << "\n";
- });
+ }
+ });
}
void ScheduleDAGMILive::
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