[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Luke Lau via llvm-commits]

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@@ -599,6 +602,10 @@ void RISCVPassConfig::addMachineSSAOptimization() {
 }
 
 void RISCVPassConfig::addPreRegAlloc() {
+  // TODO: Move this as late as possible before regalloc
+  if (TM->getOptLevel() == CodeGenOptLevel::None)
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lukel97 wrote:

At -O0 we don't run `addMachineSSAOptimization` so we still need to eliminate them here

https://github.com/llvm/llvm-project/pull/125026