[llvm] [RISCV] Select mask operands as virtual registers and eliminate vmv0 (PR #125026)

[Luke Lau via llvm-commits]

lukel97 wrote:

> One suggestion: can we stage this into two commits to make the diffs easier to understand? If you do the new pass immediately after ISEL, I think you get something which is much closer to NFC. This lets us land the majority of the cleanup Then you can do a separate change which moves it before regalloc, and we can focus on the interaction with all the passes being moved over.

I've shuffled it back to just after RISCVVectorPeephole (so we can remove the V0 def map in it), and peeked through the first COPY to match the behaviour of SelectionDAG, most of the test diffs should be gone now. 

The one place I couldn't get rid of the diffs are in the nearbyint tests. The changes are due to how the VFROUND pseudos are expanded in such a way that two pseudos might share the same $v0 COPY, instead of having one copy per pseudo, e.g.:

```
$v0 = COPY %17:vr
%41:vrm8nov0 = PseudoVFCVT_X_F_V_M8_MASK %20:vrm8nov0(tied-def 0), %0:vrm8, $v0, 7, %12:gprnox0, 6, 3, implicit $frm
%19:vrm8nov0 = PseudoVFCVT_F_X_V_M8_E64_MASK %20:vrm8nov0(tied-def 0), %41:vrm8nov0, $v0, 7, %12:gprnox0, 6, 3, implicit $frm
```

It's possible to remove redundant copies to $v0 in this pass but it ends up generating more test diffs, so shelving that idea for later.

https://github.com/llvm/llvm-project/pull/125026