[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Sander de Smalen via llvm-commits]

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@@ -1451,6 +1451,21 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // Partial Reduction nodes. These represent multiply-add instructions because
+  // Input1 and Input2 are multiplied together first. This result is then
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sdesmalen-arm wrote:

I thought the behaviour of this node is that Input1 and Input2 are first sign- (for SMLA) or zero- (for UMLA) extended to be the same element type as Acc.

nit: `Input1` and `Input2` are not defined yet. What about starting with a description of the node with operands, e.g. `PARTIAL_REDUCE_*MLA(Acc, Input1, Input2)` ?

https://github.com/llvm/llvm-project/pull/117185