[llvm] [AMDGPU] Optimizing Dynamic Alloca S-DAG I-Sel (PR #124292)

[via llvm-commits]

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@@ -4088,15 +4088,12 @@ SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
         DAG.getTargetConstant(Intrinsic::amdgcn_wave_reduce_umax, dl, MVT::i32);
     Size = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, WaveReduction,
                        Size, DAG.getConstant(0, dl, MVT::i32));
-    SDValue ScaledSize = DAG.getNode(
-        ISD::SHL, dl, VT, Size,
+    SDNode *ScaledSize = DAG.getMachineNode(
+        AMDGPU::S_LSHL_B32, dl, VT, Size,
         DAG.getConstant(Subtarget->getWavefrontSizeLog2(), dl, MVT::i32));
-    NewSP =
-        DAG.getNode(ISD::ADD, dl, VT, BaseAddr, ScaledSize); // Value in vgpr.
-    SDValue ReadFirstLaneID =
-        DAG.getTargetConstant(Intrinsic::amdgcn_readfirstlane, dl, MVT::i32);
-    NewSP = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, ReadFirstLaneID,
-                        NewSP);
+    NewSP = {DAG.getMachineNode(AMDGPU::S_ADD_I32, dl, VT, BaseAddr,
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easyonaadit wrote:

After the wave reduction is done, and all the required operands are in SGPRs, The `ISD:SHL` followed by `ISD:ADD` is being folded into a VALU instruction by a tablegen pattern. 
Then to update SP, it was leading to an illegal VGPR to SGPR copy. 
As a workaround for this, I used the readfirstlane. 
However I understand that readfirstlane is an expensive operation. With this patch I'm trying to avoid that. 

https://github.com/llvm/llvm-project/pull/124292