[llvm] [RISCV][MC] Create an AsmOperand for carry-in vmask (PR #124317)

[Craig Topper via llvm-commits]

topperc wrote:

> @mshockwave is there a reason that this had to have a dummy parse/decode of a 0-bit "field", rather than, say, a `let Uses = [V0]` on the instructions? Does llvm-mca not pay attention to implicit uses?

Would that require special handling in the AsmPrinter to remove the V0 operand which is explicit on the codegen pseudos?

The field isn't 0-bit. It's 1-bit, the `vm` bit present on all vector instructions. These instructions are different mnemonic when that bit is 1.

https://github.com/llvm/llvm-project/pull/124317