[llvm] [RISCV][MC] Create an AsmOperand for carry-in vmask (PR #124317)

[Min-Yih Hsu via llvm-commits]

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@@ -50,13 +50,25 @@ def VMaskAsmOperand : AsmOperandClass {
   let DiagnosticType = "InvalidVMaskRegister";
 }
 
+def VMaskCarryInAsmOperand : AsmOperandClass {
+  let Name = "RVVMaskCarryInRegOpOperand";
+  let RenderMethod = "addRegOperands";
+  let PredicateMethod = "isV0Reg";
+  let DiagnosticType = "InvalidVMaskCarryInRegister";
+}
+
 def VMaskOp : RegisterOperand<VMV0> {
   let ParserMatchClass = VMaskAsmOperand;
   let PrintMethod = "printVMaskReg";
   let EncoderMethod = "getVMaskReg";
   let DecoderMethod = "decodeVMaskReg";
 }
 
+def VMaskCarryInOp : RegisterOperand<VMV0> {
+  let ParserMatchClass = VMaskCarryInAsmOperand;
+  let EncoderMethod = "getVMaskReg";
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mshockwave wrote:

I'm not sure if we want to create another encoder method here. On one hand, it's impossible for codegen to create a MCOperand with register other than V0. But on the other hand, if the MCInst is created "manually", I'm not sure if it will validate the register class.

https://github.com/llvm/llvm-project/pull/124317