[llvm] [CostModel][X86] Update baseline CTTZ/CTLZ costs for x86_64 (PR #124312)
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Fri Jan 24 09:29:52 PST 2025
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git-clang-format --diff a94226f9e6f5be4d6978134e7813f22b0510f3d4 96a7660b22a4d5cabb022ddbb8b2d2fbd5653b72 --extensions cpp -- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index cdc2ce7527..9a60dd36ed 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -4325,37 +4325,38 @@ X86TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
{ ISD::CTPOP, MVT::i16, { 1, 1, 2, 2 } }, // popcnt(zext())
{ ISD::CTPOP, MVT::i8, { 1, 1, 2, 2 } }, // popcnt(zext())
};
- static const CostKindTblEntry X64CostTbl[] = { // 64-bit targets
- { ISD::ABS, MVT::i64, { 1, 2, 3, 3 } }, // SUB+CMOV
- { ISD::BITREVERSE, MVT::i64, { 10, 12, 20, 22 } },
- { ISD::BSWAP, MVT::i64, { 1, 2, 1, 2 } },
- { ISD::CTLZ, MVT::i64, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ, MVT::i32, { 1, 2, 3, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ, MVT::i16, { 2, 2, 3, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ, MVT::i8, { 2, 2, 4, 3 } }, // MOV+BSR+XOR
- { ISD::CTLZ_ZERO_UNDEF, MVT::i64,{ 1, 2, 2, 2 } }, // BSR+XOR
- { ISD::CTTZ, MVT::i64, { 1, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ, MVT::i32, { 1, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ, MVT::i16, { 2, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ, MVT::i8, { 2, 2, 2, 2 } }, // MOV+BSF
- { ISD::CTTZ_ZERO_UNDEF, MVT::i64,{ 1, 2, 1, 2 } }, // BSF
- { ISD::CTPOP, MVT::i64, { 10, 6, 19, 19 } },
- { ISD::ROTL, MVT::i64, { 2, 3, 1, 3 } },
- { ISD::ROTR, MVT::i64, { 2, 3, 1, 3 } },
- { X86ISD::VROTLI, MVT::i64, { 1, 1, 1, 1 } },
- { ISD::FSHL, MVT::i64, { 4, 4, 1, 4 } },
- { ISD::SADDSAT, MVT::i64, { 4, 4, 7, 10 } },
- { ISD::SSUBSAT, MVT::i64, { 4, 5, 8, 11 } },
- { ISD::UADDSAT, MVT::i64, { 2, 3, 4, 7 } },
- { ISD::USUBSAT, MVT::i64, { 2, 3, 4, 7 } },
- { ISD::SMAX, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::SMIN, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::UMAX, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::UMIN, MVT::i64, { 1, 3, 2, 3 } },
- { ISD::SADDO, MVT::i64, { 2, 2, 4, 6 } },
- { ISD::UADDO, MVT::i64, { 2, 2, 4, 6 } },
- { ISD::SMULO, MVT::i64, { 4, 4, 4, 6 } },
- { ISD::UMULO, MVT::i64, { 8, 8, 4, 7 } },
+ static const CostKindTblEntry X64CostTbl[] = {
+ // 64-bit targets
+ {ISD::ABS, MVT::i64, {1, 2, 3, 3}}, // SUB+CMOV
+ {ISD::BITREVERSE, MVT::i64, {10, 12, 20, 22}},
+ {ISD::BSWAP, MVT::i64, {1, 2, 1, 2}},
+ {ISD::CTLZ, MVT::i64, {1, 2, 3, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ, MVT::i32, {1, 2, 3, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ, MVT::i16, {2, 2, 3, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ, MVT::i8, {2, 2, 4, 3}}, // MOV+BSR+XOR
+ {ISD::CTLZ_ZERO_UNDEF, MVT::i64, {1, 2, 2, 2}}, // BSR+XOR
+ {ISD::CTTZ, MVT::i64, {1, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ, MVT::i32, {1, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ, MVT::i16, {2, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ, MVT::i8, {2, 2, 2, 2}}, // MOV+BSF
+ {ISD::CTTZ_ZERO_UNDEF, MVT::i64, {1, 2, 1, 2}}, // BSF
+ {ISD::CTPOP, MVT::i64, {10, 6, 19, 19}},
+ {ISD::ROTL, MVT::i64, {2, 3, 1, 3}},
+ {ISD::ROTR, MVT::i64, {2, 3, 1, 3}},
+ {X86ISD::VROTLI, MVT::i64, {1, 1, 1, 1}},
+ {ISD::FSHL, MVT::i64, {4, 4, 1, 4}},
+ {ISD::SADDSAT, MVT::i64, {4, 4, 7, 10}},
+ {ISD::SSUBSAT, MVT::i64, {4, 5, 8, 11}},
+ {ISD::UADDSAT, MVT::i64, {2, 3, 4, 7}},
+ {ISD::USUBSAT, MVT::i64, {2, 3, 4, 7}},
+ {ISD::SMAX, MVT::i64, {1, 3, 2, 3}},
+ {ISD::SMIN, MVT::i64, {1, 3, 2, 3}},
+ {ISD::UMAX, MVT::i64, {1, 3, 2, 3}},
+ {ISD::UMIN, MVT::i64, {1, 3, 2, 3}},
+ {ISD::SADDO, MVT::i64, {2, 2, 4, 6}},
+ {ISD::UADDO, MVT::i64, {2, 2, 4, 6}},
+ {ISD::SMULO, MVT::i64, {4, 4, 4, 6}},
+ {ISD::UMULO, MVT::i64, {8, 8, 4, 7}},
};
static const CostKindTblEntry X86CostTbl[] = { // 32 or 64-bit targets
{ ISD::ABS, MVT::i32, { 1, 2, 3, 3 } }, // SUB+XOR+SRA or SUB+CMOV
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https://github.com/llvm/llvm-project/pull/124312
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