[llvm] [AArch64][SME] Make getRegAllocationHints stricter for multi-vector loads (PR #123081)

[Sander de Smalen via llvm-commits]

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@@ -0,0 +1,149 @@
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs -enable-subreg-liveness -start-before=greedy %s -o - | FileCheck %s
+
+# No available group of four strided x4 registers, fall back on default allocation order
+---
+name:            form_4x_tuple_many_live
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0', virtual-reg: '%0' }
+  - { reg: '$x1', virtual-reg: '%1' }
+  - { reg: '$z0', virtual-reg: '%2' }
+  - { reg: '$z17', virtual-reg: '%3' }
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sdesmalen-arm wrote:

nit: I think you can remove these as well, because this information will be otherwise recomputed.

https://github.com/llvm/llvm-project/pull/123081